Multi-execution resource graphics processor

• US 20070030278A1
• Filed: 08/08/2005
• Published: 02/08/2007
• Est. Priority Date: 08/08/2005
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Prokopenko, Boris, Paltashev, Timour
• Granted Patent: US 7,659,898 B2
• Time in Patent Office: Days
• US Class Current: 345/506
• CPC Class Codes: G06F 9/5044 considering hardware capabilities

Abstract

A dynamically scheduled parallel graphics processor comprises a spreader that creates graphic objects for processing and assigns and distributes the created objects for processing to one or more execution blocks. Each execution block is coupled to the spreader and receives an assignment for processing a graphics. object. The execution block pushes the object through each processing stage by scheduling the processing of the graphics object and executing instruction operations on the graphics object. The dynamically scheduled parallel graphics processor includes one or more fixed function units coupled to the spreader that are configured to execute one or more predetermined operations on a graphics object. An input/output unit is coupled to the spreader, the one or more fixed function units, and the plurality of execution blocks and is configured to provide access to memory external to the dynamically scheduled parallel graphics processor.

Claims

1. A dynamically scheduled parallel graphics processor, comprising:

a spreader configured to create graphic objects to be processed and to assign and distribute the created graphic objects for processing;

a plurality of execution blocks coupled to the spreader and configured to receive an assignment for processing a graphics object from the spreader and to push the entity through one or more stages of processing, wherein each execution block schedules processing of the assigned graphics object, makes information about an assigned data object available to one or more other execution blocks, and executes one or more instruction operations on the assigned object;

one or more fixed function units coupled to the spreader and the plurality of execution blocks and configured to execute one or more predetermined operations on a graphic object; and

an input/output unit coupled to the spreader, the one or more fixed function units, and the plurality of execution blocks configured to provide access to memory external to the dynamic scheduling unit.

2. The processor of claim 1, wherein the one or more fixed function units perform rasterization, texturing, or outputting of pixel processing parts.

3. The processor of claim 1, wherein the spreader allocates vertex graphic object entities associated with a triangle graphics object entity to an execution block also assigned to process the triangle graphics object entity.

4. The processor of claim 1, further comprising:

logic in the spreader configured to maintain and update at each clock cycle for each execution block the amount of available resources, the entities being processed, physical buffer data for each entity, and available cache memory.

5. The processor of claim 1, further comprising:

logic in the spreader configured to prioritize each execution block of the plurality of execution blocks for being assigned a particular graphics object.

6. The processor of claim 1, further comprising:

logic executable by the spreader configured to establish and maintain data layout preferences for triangle graphic objects in association with corresponding vertices and pixels.

7. The processor of claim 1, wherein each of the plurality of execution blocks comprises:

a stage parser containing pointers configured to point to an object to be moved or processed;

a controller configured to manage execution of floating point and integer instructions;

a descriptor table configured to provide a registry of graphic objects being processed by the execution block; and

a data move machine configured to load and move graphic objects in the execution block and further configured to communicate with the spreader and other execution blocks.

8. The processor of claim 7, further comprising:

a rename logic table configured to provide flexible address mapping of physical buffers in a cache memory.

9. The processor of claim 7, wherein the descriptor table contains information about data relation, allocation, readiness, and current stage in association with the processing of a graphics object.

10. The processor of claim 7, wherein the pointers contained in the stage parser table point to the graphics object to be processed on each stage of a logical graphics pipeline.

11. The processor of claim 10, wherein a process associated with a stage includes a numerical process involving a execution of floating point and integer instructions.

12. The processor of claim 10, wherein a process associated with a stage includes a moving a graphics object data within the execution block, to another execution block, or to the fixed function unit.

13. The processor of claim 7, wherein the descriptor table is a content addressable memory.

14. The processor of claim 1, further comprising:

logic in the spreader configured to maintain a primitive table containing primitive ID information when a triangle entity is allocated.

15. The processor of claim 14, wherein the primitive table has a primitive ID field and an execution block field corresponding to a particular execution block where a triangle entity is allocated.

16. A method for dynamically scheduling the processing of graphics data in a logical graphics pipeline, comprising the steps of:

creating an entity associated with a packet of graphics data;

selecting an execution block based on predetermined resource requirements and allocation information;

assigning the entity to a selected execution block;

allocating the entity in the selected execution block communicating graphics data related to the entity to the selected execution block; and

pushing the entity through a plurality of processing stages.

17. The method of claim 16, wherein two or more execution blocks may be selected to perform instructions on graphics data related to the entity in parallel.

18. The method of claim 16, further comprising the step of:

indexing the graphics data in a index buffer.

19. The method of claim 16, further comprising the step of:

registering the assigned entity in a table of entities, wherein the registered entity is renamed each instance when an assignment is made to the table of entities.

20. The method-of claim 19, wherein data associated with the renamed registered entity is used for subsequent data reads for the entity in the table of entities.

21. The method of claim 19, further comprising the steps of:

pointing to an entity in the table of entities to be processed by the execution block on a next stage of processing;

processing the pointed entity according to one or more floating point or integer instructions if the entity is designated for numerical processing; and

communicating the pointed entity by a data move unit to a predetermined logical location.

22. The method of claim 21, wherein the pointed entity is communicated to a fixed function unit for a predetermined graphics processing operation.

23. The method of claim 16, wherein the graphics data associated with the entity is processed according to one or more floating point and integer instructions.

24. The method of claim 16, further comprising the step of:

communicating the processed graphics data related to the entity directly to one or more additional execution blocks if the processed graphics data is related to an entity assigned to the one or more additional execution blocks.