System and method to manage data processing stages of a logical graphics pipeline

• US 20070030279A1
• Filed: 08/08/2005
• Published: 02/08/2007
• Est. Priority Date: 08/08/2005
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Prokopenko, Boris, Paltashev, Timour
• Granted Patent: US 7,659,899 B2
• Time in Patent Office: Days
• US Class Current: 345/506
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/384 Register renaming
• CPC Class Codes: G06F 9/3856 Reordering of instructions, e.g. using queues or age tags
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/5016 the resource being the memory
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining

Abstract

A system and method to manage data processing stages of a logical graphics pipeline comprises a number of execution blocks coupled together and to a global spreader that assigns graphics data entities for execution to the execution blocks. Each execution block has an entity descriptor table containing information about an assigned graphics data entity corresponding to allocation of the entity and a current processing stage associated with the entity. Each execution block includes a stage parser configured to establish pointers for the assigned graphics data entity to be processed on a next processing stage. A numerical processing unit is included and configured to execute floating point and integer instructions in association with the assigned graphics data entity. The execution blocks include a data move unit for data loads and moves within the execution block, with the global spreader, and with other execution blocks of the plurality of execution blocks.

Claims

1. A system to manage data processing stages of a logical graphics pipeline, comprising:

a plurality of execution blocks electrically coupled together and to a global spreader that assigns graphics data entities for execution to the plurality of execution blocks, each execution block comprising;

a entity descriptor table configured to contain information about an assigned graphics data entity corresponding to allocation of the entity and a current processing stage associated with the entity;

a stage parser unit configured to establish pointers for one or more processing stages and for the assigned graphics data entity to be processed next on a processing stage;

a numerical processing unit configured to execute floating point and integer instructions in association with the assigned graphics data entity; and

a data move unit configured for data loads and moves within the execution block, with the global spreader, and with other execution blocks of the plurality of execution blocks.

2. The system of claim 1, each execution block further comprising:

a cache memory configured as a logical FIFO with memory references to one or more assigned graphics data entities.

3. The system of claim 2, wherein vertex graphics data entities remain in the cache memory until completely processed by a first execution block or copied to a second execution block processing a triangle graphics data entity associated with the vertex graphics data entities.

4. The system of claim 2, wherein pixel graphics data entities remain in the cache memory until completely processed by a first execution block or copied to a second execution block processing a triangle graphics data entity associated with the pixel graphics data entities.

5. The system of claim 1, each execution block further comprising:

a thread controller configured to support multithreading of assigned graphics data entities and to interact with the numerical processing unit.

6. The system of claim 5, wherein the thread controller is configured to receive a physical buffer address from the entity descriptor table that has a real physical address according to a rename table.

7. The system of claim 1, wherein the stage parser communicates with the entity descriptor table to determine a readiness status for an assigned graphics data entity.

8. The system of claim 1, wherein the stage parser communicates with a numerical process descriptor register table component to initiate execution of a numerical process associated with an assigned graphics data entity.

9. The system of claim 1, wherein the stage parser communicates with a move descriptor register table component to initiate execution of a data move process associated with an assigned graphics data entity, and further wherein a data move instruction is generated to the data move unit directing movement of a graphics data entity.

10. The system of claim 1, wherein the stage parser evaluates a status for entities in the entity descriptor table at each clock cycle.

11. The system of claim 1, each execution block further comprising:

a rename logic table configured to contain address rename information for flexibly map addressing physical buffers in a cache memory.

12. The system of claim 1, wherein the numerical processing unit provides simultaneous execution of floating point and integer instructions so as to process multiple data items in a single instruction multiple data stream.

13. A method for managing data processing stages of a logical graphics pipeline, comprising:

receiving at one or more execution blocks an assignment from a spreader unit to execute data corresponding to a graphics data object;

allocating a physical buffer containing data associated with the graphics data object in an entity descriptor table;

establishing one or more pointers referencing data associated with the graphics data object contained in the entity descriptor table to be processed on a next processing stage;

executing one or more floating point and integer instructions on data associated with the graphics data object in a numerical processing unit; and

moving data associated with the graphics data object within the execution block, to the global spreader, or to another of the one or more execution blocks.

14. The method of claim 13, further comprising the step of:

storing data associated with the graphics data object in a cache memory configured as a logical FIFO.

15. The method of claim 14, wherein vertex graphics data objects remain in the cache memory until completely processed by a first execution block or copied to a second execution block processing a triangle/pixel graphics data object associated with the vertex/triangle graphics data entities.

16. The method of claim 13, further comprising the steps of:

controlling the numerical processing of data related to a graphics data object upon receipt of a pointer referencing data contained in the entity descriptor table;

placing numerically processed data in a cache memory; and

renaming a cache memory location associated with the placed numerically processed data.

17. The method of claim 13,.further comprising the step of:

communicating a readiness status for data associated with a graphics data object from the entity descriptor table to a stage parser component.

18. The method of claim 13, further comprising the step of:

communicating with a numerical process descriptor register table component to initiate execution of a numerical process in association with data corresponding to the graphics data object.

19. The method of claim 13, wherein a stage parser component communicates with a move descriptor register table component to initiate execution of a data move process in association with data corresponding to the graphics data object, and further wherein a data move instruction is generated to the data move unit directing movement data corresponding to the graphics data object.

20. The method of claim 13, wherein a stage parser component evaluates a status for data in the entity descriptor table at each clock cycle.

21. The method of claim 13, further comprising the step of:

renaming physical buffers in a cache memory when data associated with the physical buffers is altered by the execution block so that a most current data is available.