Serial memory script controller

• US 20070030281A1
• Filed: 05/11/2006
• Published: 02/08/2007
• Est. Priority Date: 07/25/2005
• Status: Abandoned Application

• Current Assignee: Beyond Innovation Technology Co Ltd
• Original Assignee: Beyond Innovation Technology Co Ltd
• Inventors: Chen, Chia-Hsin
• Application Number:
  US11/431,543
• Publication Number:
  US 20070030281A1
• Time in Patent Office: Days
• US Class Current: 345/531
• CPC Class Codes: G09G 5/363 Graphics controllers

Abstract

The present invention provides an IC chip of a serial memory script controller, comprising: an interface transforming unit, an I/O buffer and data path control unit, a script decoder, an ALU and an event control unit. The interface transforming unit codes and decodes a communication protocol of a serial interface; the I/O buffer and data path control unit is electrically connected to the interface transforming unit, stores the input and output data of the interface transforming unit; and selects and controls the data path; the script decoder is electrically connected to the input/output buffer and data path control unit, and decode a program code stored in the input/output buffer and data path control unit, and then a corresponding control signal is transformed; the ALU is electrically connected to the input/output buffer and data path control unit and the script decoder, and executes an instruction operation in accordance with data of the input/output buffer and data path control unit and the script decoder; and the event control unit is electrically connected to the interface transforming unit, the input/output buffer and data path control unit, and the script decoder, and receives an event, wherein the interface transforming unit, the input/output buffer and data path control unit, and the script decoder execute processing and operation in accordance with the event. The serial memory script controller built in an IC chip to simplify the architecture inside the IC to achieve the advantages of the minification, thinning, increasing the performance, and decreasing the power consumption.

Claims

1. A serial memory script controller, comprising:

an interface transforming unit, coding and decoding a communication protocol of a serial interface;

an input/output buffer and data path control unit, electrically connected to the interface transforming unit, and storing the input and output data of the interface transforming unit and selecting and controlling a data path;

a script decoder, electrically connected to the input/output buffer and data path control unit, and decoding a program code stored in the input/output buffer and data path control unit, and then coresponsively generating a control signal;

an arithmetic logic unit (ALU), electrically connected to the input/output buffer and data path control unit and the script decoder, executing an instruction operation in accordance with data of the input/output buffer and data path control unit and the script decoder; and

an event control unit, electrically connected to the interface transforming unit, the input/output buffer and data path control unit, and the script decoder, receiving an event, wherein the interface transforming unit, the input/output buffer and data path control unit, and the script decoder execute processing and operation in accordance with the event.

2. The serial memory script controller according to the claim 1, wherein the instruction operation is selected from a logic instruction and an arithmetic operation instruction.

3. The serial memory script controller according to the claim 1, wherein the script code is selected from a logic instruction, an operation instruction, a data movement instruction, a script control, and a system instruction.

4. The serial memory script controller according to the claim 2, wherein the program code is selected from a logic instruction, an operation instruction, a data movement instruction, a script control and a system instruction.

5. The serial memory script controller according to the claim 1, wherein the event is selected from an external event, an internal event, and a special event.

6. The serial memory script controller according to the claim 2, wherein the event is selected from an external event, an internal event, and a special event.

7. The serial memory script controller according to the claim 3, wherein the event is selected from an external event, an internal event, and a special event.

8. The serial memory script controller according to the claim 4, wherein the event is selected from an external event, an internal event, and a special event.

9. A serial memory script controller, comprising:

an interface transforming unit, coding and decoding a communication protocol of serial interface, transforming a serial data into a parallel data to provide for internal use of the serial memory script controller, and transforming the internal parallel data into the serial data to output;

an input/output buffer and data path control unit, electrically connected to the interface transforming unit, storing the input and output data of the interface transforming unit, and selecting and controlling a data path;

a script decoder, electrically connected to the input/output buffer and data path control unit, and decoding a program code stored in the input/output buffer and data path control unit, and then coresponsively generating a control signal;

an arithmetic logic unit (ALU), electrically connected to the input/output buffer and data path control unit and the script decoder, executing an instruction operation in accordance with data of the input/output buffer and data path control unit and the script decoder; and

an event control unit, electrically connected to the interface transforming unit, the input/output buffer and data path control unit, and the script decoder, receiving an event, wherein the interface transforming unit, the input/output buffer and data path control unit, and the script decoder execute processing and operation in accordance with the event.

10. The serial memory script controller according to the claim 9, wherein the instruction operation is selected from a logic instruction and a arithmetic operation instruction.

11. The serial memory script controller according to the claim 9, wherein the script code is selected from a logic instruction, an operation instruction, a data movement instruction, a script control, and a system instruction.

12. The serial memory script controller according to the claim 9, wherein the event is selected from an external event, an internal event, and a special event.

13. A system circuit architecture of a graphics processor, comprising:

an image input source, providing an image;

a memory device, storing a program code;

a displaying apparatus; and

a graphics processor, electrically connected to the image input source, the memory device, and the displaying apparatus wherein the graphics processor comprises a built-in script controller to process the image and then transmit a processed result to the displaying apparatus, and the built-in script controller is electrically connected to the memory device and retrieves the program code to execute image processing.

14. The system circuit architecture of a graphics processor according to the claim 13, further comprising a key pad electrically connected to the script controller, driving the script controller to execute the program code stored in the memory device to set a required parameter of a user.

15. The system circuit architecture of a graphics processor according to the claim 13, wherein the script controller comprises:

an interface transforming unit, coding and decoding a communication protocol of serial interface;

an input/output buffer and data path control unit, electrically connected to the interface transforming unit, storing the input and output data of the interface transforming unit, and selecting and controlling a data path;

a script decoder, electrically connected to the input/output buffer and data path control unit, and decoding a program code stored in the input/output buffer and data path control unit, and then coresponsively generating a control signal;

an arithmetic logic unit (ALU), electrically connected to the input/output buffer and data path control unit and the script decoder, executing an instruction operation in accordance with data of the input/output buffer and data path control unit and the script decoder; and

an event control unit, electrically connected to the interface transforming unit, the input/output buffer and data path control unit, and the script decoder, receiving an event, wherein the interface transforming unit, the input/output buffer and data path control unit, and the script decoder execute processing and operation in accordance with the event.

16. The system circuit architecture of a graphics processor according to the claim 14, wherein the script controller comprises:

an interface transforming unit, coding and decoding a communication protocol of serial interface;

an input/output buffer and data path control unit, electrically connected to the interface transforming unit, storing the input and output data of the interface transforming unit, and selecting and controlling a data path;

a script decoder, electrically connected to the input/output buffer and data path control unit, and decode a program code stored in the input/output buffer and data path control unit, and then coresponsively generating a control signal;

an arithmetic logic unit (ALU), electrically connected to the input/output buffer and data path control unit and the script decoder, executing an instruction operation in accordance with data of the input/output buffer and data path control unit and the script decoder; and

an event control unit, electrically connected to the interface transforming unit, the input/output buffer and data path control unit, and the script decoder, receiving an event, wherein the interface transforming unit, the input/output buffer and data path control unit, and the script decoder execute processing and operation in accordance with the event.

17. The system circuit architecture of a graphics processor according to the claim. 15, wherein the instruction operation is selected from a logic instruction and an arithmetic operation instruction.

18. The system circuit architecture of a graphics processor according to the claim 16, wherein the instruction operation is selected from a logic instruction and an arithmetic operation instruction.

19. The system circuit architecture of a graphics processor according to the claim 15, wherein the script code is selected from a logic instruction, an operation instruction, a data movement instruction, a script control, and a system instruction.

20. The system circuit architecture of a graphics processor according to the claim 16, wherein the script code is selected from a logic instruction, an operation instruction, a data movement instruction, a script control, and a system instruction.

21. The system circuit architecture of a graphics processor according to the claim 15, wherein the event is selected from an external event, an internal event, and a special event.

22. The system circuit architecture of a graphics processor according to the claim 16, wherein the event is selected from an external event, an internal event, and a special event.