Semiconductor device for protecting rechargeable battery

• US 20070030614A1
• Filed: 07/31/2006
• Published: 02/08/2007
• Est. Priority Date: 08/08/2005
• Status: Active Grant

• Current Assignee: Nisshinbo Micro Devices Incorporated (Nisshinbo Holdings Incorporated)
• Original Assignee: Ricoh Company Limited
• Inventors: Fujiwara, Akihiko, Yano, Koichi
• Granted Patent: US 7,728,556 B2
• Time in Patent Office: Days
• US Class Current: 361/92
• CPC Class Codes: H02H 7/18 for batteries; for accumulators
• CPC Class Codes: H02J 7/00306 Overdischarge protection
• CPC Class Codes: H02J 7/0031 using battery or load disconnect circuits H02J9/002 takes precedence

Abstract

A semiconductor device for protecting a rechargeable cell at least from excessive discharge current due to over discharge of the rechargeable cell, includes (a) a first excessive discharge current detection circuit configured to detect first excess of a voltage at an externally or an internally provided electric current detection terminal exceeding a first voltage level (Vs3), (b) a second excessive discharge current detection circuit configured to detect second excess of the absolute voltage at the electric current detection terminal exceeding a second voltage level (Vs4) higher than the first voltage level, (c) a delay circuit configured to cause each of the first and second excessive discharge current detection circuits to delay its output by a predetermined delay time, and (d) a delay reducing circuit configured to produce a delay time reducing signal for reducing the delay time at a predetermined ratio when a negative voltage lower than a predetermined negative voltage level or a positive voltage higher than a third voltage level (Vt) is applied to the electric current detection terminal.

Claims

1. A semiconductor device for protecting a rechargeable cell at least from excessive discharge current due to over discharge of the rechargeable cell, the semiconductor device comprising:

a first excessive discharge current detection circuit configured to detect first excess of a voltage at an externally or an internally provided electric current detection terminal exceeding a first voltage level, the electric current detection terminal converting a discharge current to a positive voltage with respect to a ground potential;

a second excessive discharge current detection circuit configured to detect second excess of the absolute voltage at the electric current detection terminal exceeding a second voltage level higher than the first voltage level;

a delay circuit configured to cause each of the first and second excessive discharge current detection circuits to delay its output by a predetermined delay time; and

a delay reducing circuit configured to produce a delay time reducing signal for reducing the delay time at a predetermined ratio when a negative voltage lower than a predetermined negative voltage level or a positive voltage higher than a third voltage level is applied to the electric current detection terminal.

2. The semiconductor device of claim 1, wherein upon receiving the delay time reducing signal, the delay circuit changes the delay time at a different reducing ratio depending whether an operation is in a recharging mode or a discharging mode.

3. The semiconductor device of claim 1, wherein the third voltage level is higher than the first voltage level and is lower than the second voltage level.

4. The semiconductor device of claim 1, wherein the third voltage level is set higher than the second voltage level.

5. The semiconductor device of claim 1, wherein the delay reducing circuit includes:

a first inverter of a CMOS structure with a negative power-source terminal connected to the electric current detection terminal and an input terminal connected to the ground potential or a predetermined potential;

a second inverter of a CMOS structure with a negative power-source terminal connected to the electric current detection terminal and an input terminal connected to the output of the first inverter; and

a third inverter of CMOS structure with an input terminal connected to the output of the second inverter.

6. The semiconductor device of claim 5, wherein the predetermined negative voltage level is determined by the threshold voltage of the NMOS transistor of the first inverter, whose gate is connected to the input terminal of the first inverter, during the fabrication process.

7. The semiconductor device of claim 5, wherein the positive voltage level higher than the third voltage level is determined by the threshold voltage of the NMOS transistor of the third inverter, whose gate is connected to the input terminal of the third inverter, during the fabrication process.

8. The semiconductor device of claim 5, wherein the first inverter has a hysteresis characteristic.