Seamless coarse and fine delay structure for high performance DLL

• US 20070030753A1
• Filed: 07/21/2005
• Published: 02/08/2007
• Est. Priority Date: 07/21/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Kwak, Jongtae
• Granted Patent: US 7,629,819 B2
• Time in Patent Office: Days
• US Class Current: 365/233.110
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: H03L 7/00 Automatic control of frequency or phase; Synchronisation
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
• CPC Class Codes: H03L 7/0818 the controlled phase shifter comprising coarse and fine delay or phase-shifting means

Abstract

A clock synchronization system and method avoids output clock jitter at high frequencies and also achieves a smooth phase transition at the boundary of the coarse and fine delays. The system may use a single coarse delay line configured to generate two intermediate clocks from the input reference clock and having a fixed phase difference therebetween. The coarse delay line may have a hierarchical or a non-hierarchical structure. A phase mixer receives these two intermediate clocks and generates the final output clock having a phase between the phases of the intermediate clocks. The coarse shifting in the delay line at high clock frequencies does not affect the phase relationship between the intermediate clocks fed into the phase mixer. The output clock from the phase mixer is time synchronized with the input reference clock and does not exhibit any jitter or noise even at high clock frequency inputs. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Claims

1. A method of producing a clock signal, comprising:

applying a reference clock to a first delay unit in a single, coarse delay line, wherein said delay line includes a plurality of delay units;

generating a first intermediate clock and a second intermediate clock from said reference clock using said single delay line, wherein said first and said second intermediate clocks have a fixed phase difference therebetween; and

generating an output clock from said first and said second intermediate clocks, wherein said output clock has a phase between the phases of said first and said second intermediate clocks.

2. The method of claim 1 wherein a time value of said fixed phase difference is equal to the time delay provided by a delay unit in said delay line.

3. The method of claim 1 wherein said generating an output clock comprises:

applying said first and said second intermediate clocks to a phase mixer; and

inputting a weight factor signal to said phase mixer, said phase mixer configured to generate said output clock using said first intermediate clock, said second intermediate clock, and said weight factor signal.

4. The method of claim 3 wherein said phase mixer is configured based on the following equation:

said output clock=(said first intermediate clock)*(1−

K)+(said second intermediate clock)*(K),

wherein “

K”

is said weight factor signal.

5. The method of claim 1 wherein said single delay line is formed of a chain of serially connected delay units, a plurality of tri-state inverters is positioned such that each inverter receives the output from one of said delay units in said chain of delay units, said generating first and second intermediate clocks comprising:

selectively combining outputs of at least certain of the even-numbered tri-state inverters in said delay line to generate said first intermediate clock and selectively combining outputs of at least certain of the odd-numbered tri-state inverters in said delay line to generate said second intermediate clock.

6. The method of claim 5 wherein said selectively combining comprises:

selectively activating two or more delay units and each tri-state inverter connected to an input and an output, respectively, of the most-recently activated delay unit in said two or more delay units based on a delay determination by a phase detector; and

combining outputs of all even-numbered tri-state inverters to generate said first intermediate clock and of all odd-numbered tri-state inverters to generate said second intermediate clock.

7. The method of claim 5, wherein said selectively combining comprises:

selectively activating two or more delay units and each tri-state inverter connected to an input and an output, respectively, of the most-recently activated delay unit in said two or more delay units based on a delay determination by a phase detector;

grouping all even-numbered tri-state inverters into a plurality of first sets, wherein each of said plurality of first sets contains a predetermined number of even-numbered tri-state inverters;

grouping all odd-numbered tri-state inverters into a plurality of second sets, wherein each of said plurality of second sets contains a predetermined number of odd-numbered tri-state inverters;

combining outputs of all even-numbered tri-state inverters in each first set to generate a corresponding first set signal output of each first set and combining outputs of all odd-numbered tri-state inverters in each second set to generate a corresponding second set signal output of each second set;

supplying each first set signal output as an input to a corresponding one of a plurality of even-numbered outputting tri-state inverters and each second set signal output as an input to a corresponding one of a plurality of odd-numbered outputting tri-state inverters; and

combining outputs of all even-numbered outputting tri-state inverters to generate said first intermediate clock and of all odd-numbered outputting tri-state inverters to generate said second intermediate clock.

8. A method of producing a clock signal from a single, coarse delay line formed by a chain of serially connected delay units with a tri-state inverter positioned at the output of each delay unit in said chain of delay units, said method comprising:

applying a reference clock to a first delay unit in said coarse delay line;

starting with a pair of delay units that includes said first delay unit, selectively activating two or more delay units and each tri-state inverter connected to an input and an output, respectively, of the most-recently activated delay unit in said two or more delay units based on a delay determination by a phase detector;

combining outputs of at least certain of the even-numbered tri-state inverters in said delay line to generate said first intermediate clock and selectively combining outputs of at least certain of the odd-numbered tri-state inverters in said delay line to generate said second intermediate clock, wherein said first and said second intermediate clocks have a fixed phase difference therebetween; and

generating an output clock from said first and said second intermediate clocks, wherein said output clock has a phase between the phases of said first and said second intermediate clocks.

9. The method of claim 8 wherein a time value of said fixed phase difference is equal to the time delay provided by a delay unit in said delay line.

10. The method of claim 8 wherein said generating an output clock comprises:

applying said first and said second intermediate clocks to a phase mixer; and

inputting a weight factor signal to said phase mixer, said phase mixer configured to generate said output clock using said first intermediate clock, said second intermediate clock, and said weight factor signal.

11. The method of claim 10 wherein said phase mixer is configured based on the following equation:

said output clock=(said first intermediate clock)*(1−

K)+(said second intermediate clock)*(K),

wherein “

K”

is said weight factor signal.

12. A method of operating a synchronization circuit, comprising:

applying a reference clock to a first delay unit in a single, coarse delay line, wherein said delay line includes a plurality of delay units;

generating a first intermediate clock and a second intermediate clock from said reference clock using said single, coarse delay line, wherein said first and said second intermediate clocks have a fixed phase difference therebetween;

inputting said first and said second intermediate clocks into a fine delay unit;

generating an output clock from said first and said second intermediate clocks using said fine delay unit, wherein said output clock has a phase between the phases of said first and said second intermediate clocks; and

using said output clock as a feedback signal to control the number of delay units that are active in said coarse delay line.

13. The method of claim 12 wherein a time value of said fixed phase difference is equal to the time delay provided by a delay unit in said delay line.

14. The method of claim 12 wherein said fine delay unit is a phase mixer and wherein said generating an output clock comprises:

applying said first and said second intermediate clocks to said phase mixer; and

inputting a weight factor signal to said phase mixer, said phase mixer configured to generate said output clock using said first intermediate clock, said second intermediate clock, and said weight factor signal.

15. The method of claim 14 wherein said phase mixer is configured based on the following equation:

said output clock=(said first intermediate clock)*(1−

K)+(said second intermediate clock)*(K),

wherein “

K”

is said weight factor signal.

16. The method of claim 12 wherein said single, coarse delay line is formed of a chain of serially connected delay units, a plurality of tri-state inverters is positioned such that each inverter receives the output from one of said delay units in said chain of delay units, said generating first and second intermediate clocks comprising:

selectively combining outputs of at least certain of the even-numbered tri-state inverters in said coarse delay line to generate said first intermediate clock and selectively combining outputs of at least certain of the odd-numbered tri-state inverters in said delay line to generate said second intermediate clock.

17. The method of claim 16 wherein said selectively combining comprises:

selectively activating two or more delay units and each tri-state inverter connected to an input and an output, respectively, of the most-recently activated delay unit in said two or more delay units based on a delay determination by a phase detector; and

combining outputs of all even-numbered tri-state inverters to generate said first intermediate clock and of all odd-numbered tri-state inverters to generate said second intermediate clock.

18. The method of claim 16, wherein said selectively combining comprises:

selectively activating two or more delay units and each tri-state inverter connected to an input and an output, respectively, of the most-recently activated delay unit in said two or more delay units based on a delay determination by a phase detector;

grouping all even-numbered tri-state inverters into a plurality of first sets, wherein each of said plurality of first sets contains a predetermined number of even-numbered tri-state inverters;

grouping all odd-numbered tri-state inverters into a plurality of second sets, wherein each of said plurality of second sets contains a predetermined number of odd-numbered tri-state inverters;

combining outputs of all even-numbered tri-state inverters in each first set to generate a corresponding first set signal output of each first set and combining outputs of all odd-numbered tri-state inverters in each second set to generate a corresponding second set signal output of each second set;

supplying each first set signal output as an input to a corresponding one of a plurality of even-numbered outputting tri-state inverters and each second set signal output as an input to a corresponding one of a plurality of odd-numbered outputting tri-state inverters; and

combining outputs of all even-numbered outputting tri-state inverters to generate said first intermediate clock and of all odd-numbered outputting tri-state inverters to generate said second intermediate clock.

19. A circuit, comprising:

a single, coarse delay line for receiving a reference clock and for generating a first intermediate clock and a second intermediate clock therefrom, wherein said first and said second intermediate clocks have a fixed phase difference therebetween; and

a phase mixer coupled to said delay line to receive said first and said second intermediate clocks as inputs thereto and to generate an output clock as an output therefrom, wherein said output clock has a phase between the phases of said first and said second intermediate clocks.

20. The circuit of claim 19 wherein said delay line includes a plurality of delay units, and wherein a time value of said fixed phase difference is equal to the time delay provided by a delay unit in said delay line.

21. The circuit of claim 19 wherein said phase mixer is configured to generate said output clock based on the following equation:

said output clock=(said first intermediate clock)*(1−

K)+(said second intermediate clock)*(K),

wherein “

K”

is a weight factor signal supplied to said phase mixer.

22. The circuit of claim 19 wherein said delay line comprises:

a plurality of delay units forming a serial chain of delay units, and wherein said reference clock is applied to a first delay unit in said chain of delay units; and

a plurality of tri-state inverters each placed so as to receive an output from one of said delay units in said chain of delay units, and wherein the outputs of all even-numbered tri-state inverters are connected together to obtain said first intermediate clock and the outputs of all odd-numbered tri-state inverters are connected together to obtain said second intermediate clock.

23. The circuit of claim 19 wherein said delay line comprises:

a plurality of delay units forming a serial chain of delay units, and wherein said reference clock is applied to a first delay unit in said chain of delay units; and

a first plurality of tri-state inverters each placed so as to receive an output from one of said delay units in said chain of delay units, wherein all even-numbered tri-state inverters in said first plurality of tri-state inverters are grouped into a plurality of first sets, wherein each of said plurality of first sets contains a predetermined number of even-numbered tri-state inverters, and wherein all odd-numbered tri-state inverters in said first plurality of tri-state inverters are grouped into a plurality of second sets, wherein each of said plurality of second sets contains a predetermined number of odd-numbered tri-state inverters;

a plurality of first set signal output lines, wherein each first set signal output line is obtained from combining outputs of all even-numbered tri-state inverters in each corresponding first set;

a plurality of second set signal output lines, wherein each second set signal output line is obtained from combining outputs of all odd-numbered tri-state inverters in each corresponding second set; and

a second plurality of tri-state inverters comprising a plurality of even-numbered outputting tri-state inverters and a plurality of odd-numbered outputting tri-state inverters, wherein an input of each even-numbered outputting tri-state inverter is connected to a corresponding one of said plurality of first set signal output lines and input of each odd-numbered outputting tri-state inverter is connected to a corresponding one of said plurality of second set signal output lines, wherein the outputs of all even-numbered outputting tri-state inverters are connected together to obtain said first intermediate clock and the outputs of all odd-numbered outputting tri-state inverters are connected together to obtain said second intermediate clock.

24. A synchronization circuit, comprising:

a single, coarse delay line for receiving a reference clock and for generating a first intermediate clock and a second intermediate clock therefrom, wherein said first and said second intermediate clocks have a fixed phase difference therebetween;

a phase mixer coupled to said delay line to receive said first and said second intermediate clocks as inputs thereto and to generate an output clock as an output therefrom, wherein said output clock has a phase between the phases of said first and said second intermediate clocks; and

a feedback loop for controlling said coarse delay line.

25. The circuit of claim 24 wherein said coarse delay line includes a plurality of delay units, and wherein a time value of said fixed phase difference is equal to the time delay provided by a delay unit in said coarse delay line.

26. The circuit of claim 24 wherein said phase mixer is configured to generate said output clock based on the following equation:

said output clock=(said first intermediate clock)*(1−

K)+(said second intermediate clock)*(K),

wherein “

K”

is a weight factor signal supplied to said phase mixer.

27. The circuit of claim 24 wherein said coarse delay line comprises:

a plurality of delay units forming a serial chain of delay units, and wherein said reference clock is applied to a first delay unit in said chain of delay units; and

a plurality of tri-state inverters each placed so as to receive an output from one of said delay units in said chain of delay units, and wherein the outputs of all even-numbered tri-state inverters are connected together to obtain said first intermediate clock and the outputs of all odd-numbered tri-state inverters are connected together to obtain said second intermediate clock.

28. The circuit of claim 24 wherein said coarse delay line comprises:

a plurality of delay units forming a serial chain of delay units, and wherein said reference clock is applied to a first delay unit in said chain of delay units; and

a first plurality of tri-state inverters each placed so as to receive an output from one of said delay units in said chain of delay units, wherein all even-numbered tri-state inverters in said first plurality of tri-state inverters are grouped into a plurality of first sets, wherein each of said plurality of first sets contains a predetermined number of even-numbered tri-state inverters, and wherein all odd-numbered tri-state inverters in said first plurality of tri-state inverters are grouped into a plurality of second sets, wherein each of said plurality of second sets contains a predetermined number of odd-numbered tri-state inverters;

a plurality of first set signal output lines, wherein each first set signal output line is obtained from combining outputs of all even-numbered tri-state inverters in each corresponding first set;

a plurality of second set signal output lines, wherein each second set signal output line is obtained from combining outputs of all odd-numbered tri-state inverters in each corresponding second set; and

a second plurality of tri-state inverters comprising a plurality of even-numbered outputting tri-state inverters and a plurality of odd-numbered outputting tri-state inverters, wherein an input of each even-numbered outputting tri-state inverter is connected to a corresponding one of said plurality of first set signal output lines and input of each odd-numbered outputting tri-state inverter is connected to a corresponding one of said plurality of second set signal output lines, wherein the outputs of all even-numbered outputting tri-state inverters are connected together to obtain said first intermediate clock and the outputs of all odd-numbered outputting tri-state inverters are connected together to obtain said second intermediate clock.

29. The circuit of claim 24 wherein said feedback loop comprises:

a phase detector for receiving said reference clock and said output clock and for generating a shift indication signal based on a relationship between the phases of said reference clock and said output clock; and

a shift register coupled to said coarse delay line and said phase detector, wherein said shift register generates and outputs a shift selection signal to said coarse delay line based on said shift indication signal to thereby control the number of delay units that are active is said coarse delay line.

30. The circuit of claim 24 further comprising a control unit responsive to said phase detector for producing a weight factor signal.

31. The circuit of claim 24 wherein said phase mixer comprises:

a first set of tri-state inverters, wherein each tri-state inverter in said first set is configured to receive said first intermediate clock as an input thereto and wherein each tri-state inverter in said first set is configured to receive a corresponding weight factor signal to be applied to said first intermediate clock; and

a second set of tri-state inverters, wherein each tri-state inverter in said second set is configured to receive said second intermediate clock as an input thereto and wherein each tri-state inverter in said second set is configured to receive said corresponding weight factor signal in a manner complementary to that for a similarly-situated tri-state inverter in said first set of tri-state inverters, and wherein outputs of all tri-state inverters in said first and said second set of tri-state inverters are connected together to obtain said output clock.

32. A memory device, comprising:

a plurality of memory cells; and

a plurality of peripheral devices for writing data to and reading data from said plurality of memory cells, said peripheral devices including a synchronization circuit comprising;

a single, coarse delay line for receiving a reference clock and for generating a first intermediate clock and a second intermediate clock therefrom, wherein said first and said second intermediate clocks have a fixed phase difference therebetween;

a phase mixer coupled to said delay line to receive said first and said second intermediate clocks as inputs thereto and to generate an output clock as an output therefrom, wherein said output clock has a phase between the phases of said first and said second intermediate clocks; and

a feedback loop for controlling said coarse delay line.

33. The memory device of claim 32 wherein said coarse delay line includes a plurality of delay units, and wherein a time value of said fixed phase difference is equal to the time delay provided by a delay unit in said coarse delay line.

34. The memory device of claim 32 wherein said phase mixer is configured to generate said output clock based on the following equation:

said output clock=(said first intermediate clock)*(1−

K)+(said second intermediate clock)*(K),

wherein “

K”

is a weight factor signal supplied to said phase mixer.

35. The memory device of claim 32 wherein said coarse delay line comprises:

a plurality of delay units forming a serial chain of delay units, and wherein said reference clock is applied to a first delay unit in said chain of delay units; and

a plurality of tri-state inverters each placed so as to receive an output from one of said delay units in said chain of delay units, and wherein the outputs of all even-numbered tri-state inverters are connected together to obtain said first intermediate clock and the outputs of all odd-numbered tri-state inverters are connected together to obtain said second intermediate clock.

36. The memory device of claim 32 wherein said feedback loop comprises:

a phase detector for receiving said reference clock and said output clock and for generating a shift indication signal based on a relationship between the phases of said reference clock and said output clock; and

a shift register coupled to said coarse delay line and said phase detector, wherein said shift register generates and outputs a shift selection signal to said coarse delay line based on said shift indication signal to thereby control the number of delay units that are active is said coarse delay line.

37. The memory device of claim 36 further comprising a control unit responsive to said phase detector for producing a weight factor signal.

38. The memory device of claim 32 wherein said phase mixer comprises:

a first set of tri-state inverters, wherein each tri-state inverter in said first set is configured to receive said first intermediate clock as an input thereto and wherein each tri-state inverter in said first set is configured to receive a corresponding weight factor signal to be applied to said first intermediate clock; and

a second set of tri-state inverters, wherein each tri-state inverter in said second set is configured to receive said second intermediate clock as an input thereto and wherein each tri-state inverter in said second set is configured to receive said corresponding weight factor signal in a manner complementary to that for a similarly-situated tri-state inverter in said first set of tri-state inverters, and wherein outputs of all tri-state inverters in said first and said second set of tri-state inverters are connected together to obtain said output clock.

39. The memory device of claim 32 wherein said coarse delay line comprises:

a plurality of delay units forming a serial chain of delay units, and wherein said reference clock is applied to a first delay unit in said chain of delay units; and

a first plurality of tri-state inverters each placed so as to receive an output from one of said delay units in said chain of delay units, wherein all even-numbered tri-state inverters in said first plurality of tri-state inverters are grouped into a plurality of first sets, wherein each of said plurality of first sets contains a predetermined number of even-numbered tri-state inverters, and wherein all odd-numbered tri-state inverters in said first plurality of tri-state inverters are grouped into a plurality of second sets, wherein each of said plurality of second sets contains a predetermined number of odd-numbered tri-state inverters;

a plurality of first set signal output lines, wherein each first set signal output line is obtained from combining outputs of all even-numbered tri-state inverters in each corresponding first set;

a plurality of second set signal output lines, wherein each second set signal output line is obtained from combining outputs of all odd-numbered tri-state inverters in each corresponding second set; and

a second plurality of tri-state inverters comprising a plurality of even-numbered outputting tri-state inverters and a plurality of odd-numbered outputting tri-state inverters, wherein an input of each even-numbered outputting tri-state inverter is connected to a corresponding one of said plurality of first set signal output lines and input of each odd-numbered outputting tri-state inverter is connected to a corresponding one of said plurality of second set signal output lines, wherein the outputs of all even-numbered outputting tri-state inverters are connected together to obtain said first intermediate clock and the outputs of all odd-numbered outputting tri-state inverters are connected together to obtain said second intermediate clock.

40. A system, comprising:

a processor;

a bus; and

a memory device coupled to said processor via said bus, wherein said memory device comprises a plurality of memory cells and a plurality of peripheral devices for writing data to and reading data from said plurality of memory cells, said peripheral devices including a synchronization circuit comprising;

a single, coarse delay line for receiving a reference clock and for generating a first intermediate clock and a second intermediate clock therefrom, wherein said first and said second intermediate clocks have a fixed phase difference therebetween;

a phase mixer coupled to said delay line to receive said first and said second intermediate clocks as inputs thereto and to generate an output clock as an output therefrom, wherein said output clock has a phase between the phases of said first and said second intermediate clocks; and

a feedback loop for controlling said coarse delay line.

41. The system of claim 40 wherein said coarse delay line includes a plurality of delay units, and wherein a time value of said fixed phase difference is equal to the time delay provided by a delay unit in said coarse delay line.

42. The system of claim 40 wherein said phase mixer is configured to generate said output clock based on the following equation:

said output clock=(said first intermediate clock)*(1−

K)+(said second intermediate clock)*(K),

wherein “

K”

is a weight factor signal supplied to said phase mixer.

43. The system of claim 40 wherein said coarse delay line comprises:

a plurality of delay units forming a serial chain of delay units, and wherein said reference clock is applied to a first delay unit in said chain of delay units; and

a plurality of tri-state inverters each placed so as to receive an output from one of said delay units in said chain of delay units, and wherein the outputs of all even-numbered tri-state inverters are connected together to obtain said first intermediate clock and the outputs of all odd-numbered tri-state inverters are connected together to obtain said second intermediate clock.

44. The system of claim 40 wherein said feedback loop comprises:

a phase detector for receiving said reference clock and said output clock and for generating a shift indication signal based on a relationship between the phases of said reference clock and said output clock; and

a shift register coupled to said coarse delay line and said phase detector, wherein said shift register generates and outputs a shift selection signal to said coarse delay line based on said shift indication signal to thereby control the number of delay units that are active is said coarse delay line.

45. The system of claim 44 further comprising a control unit responsive to said phase detector for producing a weight factor signal.

46. The system of claim 40 wherein said phase mixer comprises:

a first set of tri-state inverters, wherein each tri-state inverter in said first set is configured to receive said first intermediate clock as an input thereto and wherein each tri-state inverter in said first set is configured to receive a corresponding weight factor signal to be applied to said first intermediate clock; and

a second set of tri-state inverters, wherein each tri-state inverter in said second set is configured to receive said second intermediate clock as an input thereto and wherein each tri-state inverter in said second set is configured to receive said corresponding weight factor signal in a manner complementary to that for a similarly-situated tri-state inverter in said first set of tri-state inverters, and wherein outputs of all tri-state inverters in said first and said second set of tri-state inverters are connected together to obtain said output clock.

47. The system of claim 40 wherein said coarse delay line comprises:

a plurality of delay units forming a serial chain of delay units, and wherein said reference clock is applied to a first delay unit in said chain of delay units; and

a first plurality of tri-state inverters each placed so as to receive an output from one of said delay units in said chain of delay units, wherein all even-numbered tri-state inverters in said first plurality of tri-state inverters are grouped into a plurality of first sets, wherein each of said plurality of first sets contains a predetermined number of even-numbered tri-state inverters, and wherein all odd-numbered tri-state inverters in said first plurality of tri-state inverters are grouped into a plurality of second sets, wherein each of said plurality of second sets contains a predetermined number of odd-numbered tri-state inverters;

a plurality of first set signal output lines, wherein each first set signal output line is obtained from combining outputs of all even-numbered tri-state inverters in each corresponding first set;

a plurality of second set signal output lines, wherein each second set signal output line is obtained from combining outputs of all odd-numbered tri-state inverters in each corresponding second set; and

a second plurality of tri-state inverters comprising a plurality of even-numbered outputting tri-state inverters and a plurality of odd-numbered outputting tri-state inverters, wherein an input of each even-numbered outputting tri-state inverter is connected to a corresponding one of said plurality of first set signal output lines and input of each odd-numbered outputting tri-state inverter is connected to a corresponding one of said plurality of second set signal output lines, wherein the outputs of all even-numbered outputting tri-state inverters are connected together to obtain said first intermediate clock and the outputs of all odd-numbered outputting tri-state inverters are connected together to obtain said second intermediate clock.