Performance adaptive video encoding with concurrent decoding
First Claim
1. An apparatus comprising:
- an encoder circuit configured to (i) generate one or more first status signals in response to one or more report signals and (ii) perform video encoding tasks based on available central processing unit (CPU) cycles and memory bandwidth;
a task scheduler circuit configured to (i) generate a control signal and said one or more report signals in response to said one or more first status signals; and
a decoder circuit configured to (i) generate one or more second status signals and (ii) perform concurrent decoding while said encoder circuit perform adaptive video encoding tasks in response to said control signal.
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Abstract
An encoder circuit, a task scheduler circuit and a decoder circuit. The encoder circuit may be configured to (i) generate one or more first status signals in response to one or more report signals and (ii) perform video encoding tasks based on available central processing unit (CPU) cycles and memory bandwidth. The task scheduler circuit may be configured to (i) generate a control signal and the one or more report signals in response to the one or more first status signals. The decoder circuit may be configured to (i) generate one or more second status signals and (ii) perform concurrent decoding while the encoder circuit perform adaptive video encoding tasks in response to the control signal.
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Citations
18 Claims
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1. An apparatus comprising:
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an encoder circuit configured to (i) generate one or more first status signals in response to one or more report signals and (ii) perform video encoding tasks based on available central processing unit (CPU) cycles and memory bandwidth;
a task scheduler circuit configured to (i) generate a control signal and said one or more report signals in response to said one or more first status signals; and
a decoder circuit configured to (i) generate one or more second status signals and (ii) perform concurrent decoding while said encoder circuit perform adaptive video encoding tasks in response to said control signal. - View Dependent Claims (2)
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3. An apparatus comprising:
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means for generating one or more first status signals in response to one or more report signals;
means for performing video encoding tasks based on available central processing unit (CPU) cycles and memory bandwidth;
means for generating a control signal and said one or more report signals in response to said one or more first status signals;
means for generating one or more second status signals; and
means for concurrently decoding while adaptively encoding tasks in response to said control signal.
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4. A method for adaptive video encoding, comprising the steps of:
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(A) reporting central processing unit (CPU) cycles and memory bandwidth of a plurality of processors to a video encoder;
(B) selecting one or more video encoder tasks based on the availability of said CPU cycles and said memory bandwidth; and
(C) executing said one or more video encoder tasks. - View Dependent Claims (5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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Specification