Performance adaptive video encoding with concurrent decoding

• US 20070030898A1
• Filed: 08/02/2005
• Published: 02/08/2007
• Est. Priority Date: 08/02/2005
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Cote, Guy
• Granted Patent: US 8,031,766 B2
• Time in Patent Office: Days
• US Class Current: 375/240.120
• CPC Class Codes: H04N 19/103 Selection of coding mode or of prediction mode
• CPC Class Codes: H04N 19/156 Availability of hardware or computational resources, e.g. encoding based on power-saving criteria
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/61 in combination with predictive coding

Abstract

An encoder circuit, a task scheduler circuit and a decoder circuit. The encoder circuit may be configured to (i) generate one or more first status signals in response to one or more report signals and (ii) perform video encoding tasks based on available central processing unit (CPU) cycles and memory bandwidth. The task scheduler circuit may be configured to (i) generate a control signal and the one or more report signals in response to the one or more first status signals. The decoder circuit may be configured to (i) generate one or more second status signals and (ii) perform concurrent decoding while the encoder circuit perform adaptive video encoding tasks in response to the control signal.

Claims

1. An apparatus comprising:

an encoder circuit configured to (i) generate one or more first status signals in response to one or more report signals and (ii) perform video encoding tasks based on available central processing unit (CPU) cycles and memory bandwidth;

a task scheduler circuit configured to (i) generate a control signal and said one or more report signals in response to said one or more first status signals; and

a decoder circuit configured to (i) generate one or more second status signals and (ii) perform concurrent decoding while said encoder circuit perform adaptive video encoding tasks in response to said control signal.

2. The apparatus according to claim 1, wherein said encoder circuit comprises:

a motion estimation task configured to execute a motion estimation program based on available CPU cycles and memory bandwidth;

a mode decision task configured to execute a mode decision program based on available CPU cycles and memory bandwidth; and

a pre-processing task configured to execute a pre-processing program based on available CPU cycles and memory bandwidth.

3. An apparatus comprising:

means for generating one or more first status signals in response to one or more report signals;

means for performing video encoding tasks based on available central processing unit (CPU) cycles and memory bandwidth;

means for generating a control signal and said one or more report signals in response to said one or more first status signals;

means for generating one or more second status signals; and

means for concurrently decoding while adaptively encoding tasks in response to said control signal.

4. A method for adaptive video encoding, comprising the steps of:

(A) reporting central processing unit (CPU) cycles and memory bandwidth of a plurality of processors to a video encoder;

(B) selecting one or more video encoder tasks based on the availability of said CPU cycles and said memory bandwidth; and

(C) executing said one or more video encoder tasks.

5. The method according to claim 4, wherein step (C) further comprises the step of:

collecting said CPU cycles and said memory bandwidth from said plurality of processors.

6. The method according to claim 5, further comprising the step of:

repeating step (A) in response to collecting said CPU cycle and said memory bandwidth.

7. The method according to claim 4, wherein step (B further comprises the step of:

selecting a motion estimation task based on the availability of said CPU cycles and said memory bandwidth.

8. The method according to claim 4, wherein step (B) further comprises the step of:

selecting a mode decision task based on the availability of said CPU cycles and said memory bandwidth.

9. The method according to claim 4, wherein step (B) further comprises the step of:

selecting a pre-processing task based on the availability of said CPU cycles and said memory bandwidth.

10. The method according to claim 4, wherein step (C) further comprises the step of:

executing a motion estimation program.

11. The method according to claim 10, further comprising the step of:

reporting said CPU cycles and said memory bandwidth in response to executing said motion estimation program.

12. The method according to claim 4, wherein step (C) further comprises the step of:

executing a mode decision task.

13. The method according to claim 12, further comprising the step of:

reporting said CPU cycles and said memory bandwidth in response to executing said mode decision tasks.

14. The method according to claim 4, wherein step (C) further comprises the step of:

executing a pre-processing task.

15. The method according to claim 14, further comprising the step of:

reporting said CPU cycles and said memory bandwidth in response to executing said pre-processing task.

16. The method according to claim 4, wherein step (C) further comprises the step of:

concurrently decoding a video stream.

17. The method according to claim 16, further comprising the step of:

collecting said CPU cycles and said memory bandwidth from a plurality of processors while decoding said video stream.

18. The method according to claim 4, further comprising the step of:

performing adaptive video encoding while concurrently decoding a video stream.