Video bitstream transcoding method and apparatus

• US 20070030905A1
• Filed: 08/05/2005
• Published: 02/08/2007
• Est. Priority Date: 08/05/2005
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Cote, Guy
• Granted Patent: US 8,208,540 B2
• Time in Patent Office: Days
• US Class Current: 375/240.160
• CPC Class Codes: H04N 19/112 according to a given display mode, e.g. for interlaced or progressive display mode
• CPC Class Codes: H04N 19/16 for a given display mode, e.g. for interlaced or progressive display mode
• CPC Class Codes: H04N 19/176 the region being a block, e.g. a macroblock
• CPC Class Codes: H04N 19/40 using video transcoding, i.e. partial or full decoding of a coded input stream followed by re-encoding of the decoded output stream
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/513 Processing of motion vectors
• CPC Class Codes: H04N 19/61 in combination with predictive coding

Abstract

A video transcoder is disclosed. The video transcoder generally comprises a processor and a video digital signal processor. The processor may be formed on a first die. The video digital signal processor may be formed on a second die and coupled to the processor. The video digital signal processor may have (i) a first module configured to perform a first operation in decoding an input video stream in a first format and (ii) a second module configured to perform a second operation in coding an output video stream in a second format, wherein the first operation and the second operation are performed in parallel.

Claims

1. A video transcoder comprising:

a processor formed on a first die; and

a video digital signal processor formed on a second die and coupled to said processor, said video digital-signal processor having (i) a first module configured to perform a first operation in decoding an input video stream in a first format and (ii) a second module configured to perform a second operation in coding an output video stream in a second format, wherein said first operation and said second operation are performed in parallel.

2. The video transcoder according to claim 1, wherein said first operation comprises a first macroblock reconstruction in decoding said input video stream and said second operation comprises a second macroblock reconstruction in coding said output video stream.

3. The video transcoder according to claim 1, wherein said first operation comprises an inverse transform in decoding said input video stream and said second operation comprises a forward transform in coding said output video stream.

4. The video transcoder according to claim 1, wherein said first operation comprises a first motion vector reconstruction in decoding said input video stream and said second operation comprises a second motion vector reconstruction in coding said output video stream.

5. The video transcoder according to claim 1, further comprising a memory module formed on said second die and arranged to transfer pixel information from said first module directly to said second module.

6. The video transcoder according to claim 1, wherein said first operation comprises a first motion compensation in decoding said input video stream and said second operation comprises a second motion compensation in coding said output video stream.

7. The video transcoder according to claim 1, wherein said first module is further configured to perform a third operation in coding said output video stream.

8. The video transcoder according to claim 7, wherein said first operation is a first motion compensation in decoding said input video stream and said third operation is a second motion compensation in coding said output video stream, wherein said second motion compensation is performed serially after said first motion compensation.

9. A video transcoder comprising:

a processor formed on a first die; and

a video digital signal processor formed on a second die and coupled to said processor, said video digital signal processor having (i) a decoder module configured to generate a plurality of indicators by decoding an input video stream in a first format and (ii) an encoder module configured to code an output video stream in a second format using said indicators.

10. The video transcoder according to claim 9, wherein said plurality of indicators comprise a plurality of field/frame mode indicators determined from said input video stream.

11. The video transcoder according to claim 9, wherein said plurality of indicators comprise a plurality of motion compensation mode indicators determined from said input video stream.

12. The video transcoder according to claim 9, wherein said plurality of indicators comprise a plurality of coefficient scan orders determined from said input video stream.

13. The video transcoder according to claim 9, wherein said plurality of indicators are determined from said input video stream.

14. A video transcoder comprising:

a processor formed on a first die; and

a video digital signal processor formed on a second die and coupled to said processor, said video digital signal processor having (i) a decoder module configured to decode an input video stream in a first format, (ii) an encoder module configured to code an output video stream in a second format and (iii) a memory module disposed between said decoder module and said encoder module and arranged to pass decoded pixel information from said decoder module directly to said encoder module.

15. The video transcoder according to claim 14, wherein said first format consists of an H.264 format and said second format consists of an MPEG-2 format.

16. The video transcoder according to claim 14, wherein said first format consists of an VC-1 format and said second format consists of an MPEG-2 format.

17. The video transcoder according to claim 14, wherein said first format consists of an MPEG-2 format and said second format consists of an H.264 format.

18. The video transcoder according to claim 14, wherein said first format consists of an MPEG-2 format and said second format consists of a VC-1 format.

19. The video transcoder according to claim 14, wherein said first format consists of an H.264 format and said second format consists of a VC-1 format.

20. The video transcoder according to claim 14, wherein said first format comprises a VC-1 format and said second format comprises an H.264 format.