Methods of forming memory circuitry

• US 20070032011A1
• Filed: 08/02/2005
• Published: 02/08/2007
• Est. Priority Date: 08/02/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Mathew, Suraj, Cole, Steve, Parekh, Kunal
• Granted Patent: US 7,462,534 B2
• Time in Patent Office: Days
• US Class Current: 438/238
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/48 Data lines or contacts therefor
• CPC Class Codes: H10B 12/488 Word lines

Abstract

The invention includes methods of forming memory circuitry. In one implementation, a substrate is provided which has a memory array circuitry area and a peripheral circuitry area. The memory array circuitry area comprises transistor gate lines having a first minimum line spacing. The peripheral circuitry area comprises transistor gate lines having a second minimum line spacing which is greater than the first minimum line spacing. Anisotropically etched insulative sidewall spacers are formed over opposing sidewalls of individual of said transistor gate lines within the peripheral circuitry area prior to forming anisotropically etched insulative sidewall spacers over opposing sidewalls of individual of said transistor gate lines within the memory array area. Other aspects and implementations are contemplated.

Claims

1. A method of forming memory circuitry, comprising:

providing a substrate having a memory array circuitry area and a peripheral circuitry area, the memory array circuitry area comprising transistor gate lines having a first minimum line spacing, the peripheral circuitry area comprising transistor gate lines having a second minimum line spacing which is greater than the first minimum line spacing; and

forming anisotropically etched insulative sidewall spacers over opposing sidewalls of individual of said transistor gate lines within the peripheral circuitry area prior to forming anisotropically etched insulative sidewall spacers over opposing sidewalls of individual of said transistor gate lines within the memory array area.

2. The method of claim 1 wherein the memory circuitry comprises DRAM circuitry.

3. The method of claim 1 wherein said transistor gate lines within the memory array circuitry area are void of floating gates.

4. The method of claim 1 wherein said insulative sidewall spacers within the memory array circuitry area comprise at least one of silicon nitride, aluminum oxide, and hafnium oxide.

5. The method of claim 1 wherein said insulative sidewall spacers within the peripheral circuitry area comprise undoped silicon dioxide.

6. The method of claim 5 wherein said insulative sidewall spacers within the memory array circuitry area comprise at least one of silicon nitride, aluminum oxide, and hafnium oxide.

7. The method of claim 1 wherein said insulative sidewall spacers within the peripheral circuitry area have maximum widths which are greater than maximum widths of said insulative sidewall spacers within the memory array circuitry area.

8. The method of claim 1 comprising after forming said insulative sidewall spacers within the peripheral circuitry area and said insulative sidewall spacers within the memory array circuitry area, epitaxially growing semiconductive material adjacent said insulative sidewall spacers within the memory array circuitry area.

9. The method of claim 1 comprising after forming said insulative sidewall spacers within the peripheral circuitry area and said insulative sidewall spacers within the memory array circuitry area, epitaxially growing semiconductive material adjacent said insulative sidewall spacers within the memory array circuitry area while not epitaxially growing semiconductive material adjacent said insulative sidewall spacers within the peripheral circuitry area.

10. A method of forming memory circuitry, comprising:

providing a substrate having a memory array circuitry area and a peripheral circuitry area, the memory array circuitry area comprising transistor gate lines having a first minimum line spacing, the peripheral circuitry area comprising transistor gate lines having a second minimum line spacing which is greater than the first minimum line spacing;

masking spaces between the transistor gate lines within the memory array circuitry area while forming anisotropically etched insulative sidewall spacers over the transistor gate lines within the peripheral circuitry area and not within said spaces between the transistor gate lines within the memory array circuitry area; and

masking spaces between the transistor gate lines within the peripheral circuitry area while forming anisotropically etched insulative sidewall spacers over the transistor gate lines within the memory array circuitry area and not within said spaces between the transistor gate lines within the peripheral circuitry area.

11. The method of claim 10 wherein said masking within the memory array circuitry area comprises using as a mask a layer from which said insulative sidewall spacers in the peripheral circuitry area are anisotropically etched.

12. The method of claim 10 wherein said masking within the memory array circuitry area comprises using as a mask a layer from which said insulative sidewall spacers in the peripheral circuitry area are anisotropically etched and using as a mask a layer from which said insulative sidewall spacers in the memory array circuitry area are anisotropically etched.

13. The method of claim 10 wherein said masking within the memory array circuitry area occurs before said masking within the peripheral circuitry area.

14. The method of claim 10 wherein said masking within the peripheral circuitry area occurs before said masking within the memory array circuitry area.

15. The method of claim 10 wherein said insulative sidewall spacers within the peripheral circuitry area have maximum widths which are greater than maximum widths of said insulative sidewall spacers within the memory array circuitry area.

16. A method of forming memory circuitry, comprising:

providing a substrate having a memory array circuitry area and a peripheral circuitry area, the memory array circuitry area comprising transistor gate lines having a first minimum line spacing, the peripheral circuitry area comprising transistor gate lines having a second minimum line spacing which is greater than the first minimum line spacing;

forming first insulative spacer material over the transistor gate lines within the memory array circuitry area and the peripheral circuitry area;

forming second insulative spacer material over the first insulative spacer material and over the transistor gate lines within the memory array circuitry area and the peripheral circuitry area, the second insulative spacer material being selectively etchable relative to the first insulative spacer material, the second insulative spacer material filling spaces between the transistor gate lines within the memory array circuitry area and not filling spaces between the transistor gate lines within the peripheral circuitry area;

anisotropically etching the second insulative spacer material selectively relative to the first insulative spacer material effective to form insulative sidewall spacers over opposing sidewalls of individual of said transistor gate lines within the peripheral circuitry area;

after forming said sidewall spacers within the peripheral circuitry area, etching the second insulative spacer material selectively relative to the first insulative spacer material within the memory array circuitry area while said sidewall spacers within the peripheral circuitry area are masked; and

anisotropically etching the first insulative spacer material effective to form insulative sidewall spacers over opposing sidewalls of individual of said transistor gate lines within the memory array circuitry area.

17. The method of claim 16 wherein the first insulative spacer material comprises at least one of silicon nitride, aluminum oxide, and hafnium oxide.

18. A method of forming memory circuitry, comprising:

providing a substrate having a memory array circuitry area and a peripheral circuitry area, the memory array circuitry area comprising transistor gate lines having a first minimum line spacing, the peripheral circuitry area comprising transistor gate lines having a second minimum line spacing which is greater than the first minimum line spacing; and

forming elevated source/drain regions comprising epitaxially grown semiconductive material within spaces between the transistor gate lines within the memory array circuitry area and not within spaces between the transistor gate lines within the peripheral circuitry area.

19. The method of claim 18 wherein the epitaxially grown semiconductive material spans the spaces between the transistor gate lines within the memory array circuitry area in at least one cross section.

20. The method of claim 18 wherein the memory circuitry comprises DRAM circuitry.

21. The method of claim 18 wherein said transistor gate lines within the memory array circuitry area are void of floating gates.

22. The method of claim 18 wherein,

the epitaxially grown semiconductive material spans the spaces between the transistor gate lines within the memory array circuitry area in at least one cross section;

and

the memory circuitry comprises DRAM circuitry.