Method and structure for fabricating devices using one or more films provided by a layer transfer process and etch back

• US 20070032044A1
• Filed: 08/08/2005
• Published: 02/08/2007
• Est. Priority Date: 08/08/2005
• Status: Abandoned Application

• Current Assignee: Silicon Genesis
• Original Assignee: Silicon Genesis
• Inventors: Henley, Francois
• Application Number:
  US11/199,987
• Publication Number:
  US 20070032044A1
• Time in Patent Office: Days
• US Class Current: 438/459
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Abstract

A method for fabricating one or more devices using semiconductor substrate with a cleave region. The method includes providing a substrate. In a preferred embodiment, the substrate has a thickness of semiconductor material and a surface region. In a specific embodiment, the substrate also has a cleave plane (including a plurality of particles, deposited material, or any combination of these, and the like) provided within the substrate, which defines the thickness of semiconductor material. The method includes joining the surface region of the substrate to a first handle substrate. In a preferred embodiment, the method includes initiating a controlled cleaving action at a portion of the cleave plane to detach the thickness of semiconductor material from the substrate, while the thickness of semiconductor material remains joined to the first handle substrate. The method includes processing the first handle substrate with the thickness of semiconductor material using one or more processes to form at least one integrated circuit device onto a portion of the thickness of semiconductor material. In a preferred embodiment, the processing includes high temperature semiconductor processing techniques to form conventional integrated circuits thereon. The method forms a planarized surface region overlying the thickness of semiconductor material. The method also joins the planarized surface region to a face of a second handle substrate. The method selectively removing the first handle substrate from the thickness of semiconductor material, while the face of the second handle substrate remains joined to the planarized surface region.

Claims

1. A method for fabricating one or more devices, the method comprising:

providing a substrate, the substrate having a thickness of semiconductor material and a surface region, the substrate also having a cleave plane provided within the substrate and defining the thickness of semiconductor material;

joining the surface region of the substrate to a first handle substrate;

initiating a controlled cleaving action at a portion of the cleave plane to cause a detachment of the thickness of semiconductor material from the substrate, while the thickness of semiconductor material remains joined to the first handle substrate;

processing the first handle substrate with the thickness of semiconductor material using one or more processes to form at least one integrated circuit device onto a portion of the thickness of semiconductor material;

forming a planarized surface region overlying the thickness of semiconductor material;

joining the planarized surface region to a face of a second handle substrate; and

selectively removing the first handle substrate from the thickness of semiconductor material, while the face of the second handle substrate remains joined to the planarized surface region.

2. The method of claim 1 wherein the substrate is a silicon wafer.

3. The method of claim 1 wherein the substrate comprises a silicon bearing material.

4. The method of claim 1 wherein the thickness of semiconductor material is single crystal silicon material.

5. The method of claim 1 wherein the substrate comprises at least one layer.

6. The method of claim 1 wherein the substrate comprises a multilayered structure.

7. The method of claim 1 wherein the cleave plane comprises a plurality of particles.

8. The method of claim 1 wherein the cleave plane comprises a plurality of hydrogen bearing particles.

9. The method of claim 1 wherein the cleave plane comprises a strained region.

10. The method of claim 1 wherein the cleave plane comprises a deposited material.

11. The method of claim 1 wherein the cleave plane comprises a weakened region.

12. The method of claim 1 wherein the controlled cleaving action forms a single propagating cleave front on the portion of the cleave plane to detach the thickness of material from the substrate.

13. The method of claim 1 wherein the controlled cleaving action forms more than one propagating cleave fronts on the portion of the cleave plane to detach the thickness of material from the substrate.

14. The method of claim 1 wherein the joining of the surface region of the substrate to the first handle substrate is provided by a bonding process.

15. The method of claim 1 wherein the joining comprises a plasma activation bonding process.

16. The method of claim 1 wherein the joining comprises a bonding process selected from a glue process, an electro static process, a wet activation process, an anodic process, and an inorganic glue process.

17. The method of claim 1 wherein the first handle substrate comprises a glass material.

18. The method of claim 1 wherein the first handle substrate comprises a quartz material.

19. The method of claim 1 wherein the first handle substrate is selected from a glass plate, a quartz substrate, a conductive material, a composite material, a semiconductor material, a polymer material, a metal material, and a non-organic composite material.

20. The method of claim 1 wherein the one integrated circuit device comprises a MOSFET.

21. The method of claim 1 wherein the one integrated circuit device comprises a CMOS device.

22. The method of claim 1 wherein the one integrated circuit device is selected from a bipolar device, a CMOS device, a MOSFET, and a thin film transistor.

23. The method of claim 1 wherein the second handle substrate is selected from a semiconductor substrate, a silicon substrate, a quartz substrate, a glass substrate, a metal substrate, and a polymer substrate.

24. The method of claim 1 wherein the planarized surface region comprises an oxide bearing material.

25. The method of claim 1 wherein the planarized surface region is selected provided by a chemical mechanical polishing process, a reflow process, an etch back process, or a deposition process.

26. The method of claim 1 wherein the selectively removing comprises a selective etching process to remove the first handle substrate from the thickness of semiconductor material.

27. The method of claim 1 wherein the selectively removing comprises a selective etching process using a fluoride bearing species to remove the first handle substrate from the thickness of semiconductor material.

28. A method for fabricating one or more devices using a layer transfer process, the method comprising:

providing a semiconductor substrate, the semiconductor substrate having a thickness of semiconductor material and a surface region, the semiconductor substrate also having a cleave plane including a plurality of hydrogen species provided within the semiconductor substrate and defining the thickness of semiconductor material;

joining the surface region of the semiconductor substrate to a first handle substrate;

initiating a cleaving action at a portion of the cleave plane to cause detachment of the thickness of semiconductor material from the semiconductor substrate, while the thickness of semiconductor material remains joined to the first handle substrate;

processing the first handle substrate with the thickness of semiconductor material using one or more processes to form at least one integrated circuit device onto a portion of the thickness of semiconductor material;

forming a planarized surface region overlying the thickness of semiconductor material, the planarized surface region being capable of a bonding process;

joining the planarized surface region using at least a bonding process to a face of a second handle substrate; and

selectively removing the first handle substrate from the thickness of semiconductor material, while the face of the second handle substrate remains joined to the planarized surface region.

29. The method of claim 28 wherein the semiconductor substrate is a silicon wafer.

30. The method of claim 28 wherein the semiconductor substrate comprises a silicon bearing material.

31. The method of claim 28 wherein the thickness of semiconductor material is single crystal silicon material.

32. The method of claim 28 wherein the semiconductor substrate comprises at least one layer.

33. The method of claim 28 wherein the semiconductor substrate comprises a multilayered structure.

34. The method of claim 28 wherein the cleave plane comprises a strained region.

35. The method of claim 28 wherein the cleave plane comprises a deposited material.

36. The method of claim 28 wherein the cleave plane comprises a weakened region.

37. The method of claim 28 wherein the cleaving action comprises a controlled cleaving action to form a single propagating cleave front on the portion of the cleave plane to detach the thickness of material from the substrate.

38. The method of claim 37 wherein the controlled cleaving action forms more than one propagating cleave fronts on the portion of the cleave plane to detach the thickness of material from the substrate.

39. The method of claim 28 wherein the joining of the surface region of the substrate to the first handle substrate is provided by a thermal bonding process.

40. The method of claim 28 wherein the joining comprises a plasma activation bonding process.

41. The method of claim 28 wherein the bonding process selected from a glue process, an electro static process, a wet activation process, an anodic process, and an inorganic glue process.

42. The method of claim 28 wherein the first handle substrate comprises a glass material.

43. The method of claim 28 wherein the first handle substrate comprises a quartz material.

44. The method of claim 28 wherein the first handle substrate is selected from a glass plate, a quartz substrate, a conductive material, a composite material, a semiconductor material, a polymer material, a metal material, and a non-organic composite material.

45. The method of claim 28 wherein the one integrated circuit device comprises a MOSFET.

46. The method of claim 28 wherein the one integrated circuit device comprises a CMOS device.

47. The method of claim 28 wherein the one integrated circuit device is selected from a bipolar device, a CMOS device, a MOSFET, and a thin film transistor.

48. The method of claim 28 wherein the second handle substrate is selected from a semiconductor substrate, a silicon substrate, a quartz substrate, a glass substrate, a metal substrate, and a polymer substrate.

49. The method of claim 28 wherein the planarized surface region comprises an oxide bearing material.

50. The method of claim 28 wherein the planarized surface region is selected provided by a chemical mechanical polishing process, a reflow process, an etch back process, or a deposition process.

51. The method of claim 28 wherein the selectively removing comprises a selective etching process to remove the first handle substrate from the thickness of semiconductor material.

52. The method of claim 28 wherein the selectively removing comprises a selective etching process using a fluoride bearing species to remove the first handle substrate from the thickness of semiconductor material.