Display device and driving device and driving method thereof

• US 20070033016A1
• Filed: 07/19/2006
• Published: 02/08/2007
• Est. Priority Date: 07/25/2005
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Sang-Hoon, Moon, Kook-Chul, Maeng, Ho-Suk, Choi, Pil-Mo, Song, Seock-Cheon, Kim, Ung-Sik, Park, Keun-Woo
• Granted Patent: US 7,821,508 B2
• Time in Patent Office: Days
• US Class Current: 704/219
• CPC Class Codes: G09G 3/3611 Control of matrices with row and column drivers
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence

Abstract

A driving apparatus for a display device includes a signal controller synthesizing first and second signals, respectively, having first and second signal levels to output a synthesized signal having third to fifth signal levels, a signal extracting unit extracting the first and second control signals from the synthesized signal, a gate driver generating gate signals based on the first control signal, and a data driver generating data signals based on the second control signal.

Claims

1. A driving apparatus for a display device, comprising:

a signal controller synthesizing first and second signals, respectively, having first and second signal levels to output a synthesized signal having third to fifth signal levels;

a signal extracting unit extracting the first and second control signals from the synthesized signal;

a gate driver generating gate signals based on the first control signal; and

a data driver generating data signals based on the second control signal.

2. The driving apparatus of claim 1, wherein the synthesized signal is generated on the basis of combinations of the signal levels of the first and second control signals.

3. The driving apparatus of claim 1, wherein the first and second control signals have the same signal level as each other with respect to one signal level of the third to fifth signal levels.

4. The driving apparatus of claim 1, wherein the third to fifth signal levels are a high level, a middle level, and a low level, respectively, and when the synthesized signal has the middle level, the first and second control signals have signal levels that are equal to each other.

5. The driving apparatus of claim 1, wherein when the first and second control signals have the first signal level, the synthesized signal has the third signal level, when the first control signal has the first signal level and the second control signal has the second signal level, the synthesized signal has the fourth signal level, when the first control signal has the second signal level and the second control signal has the first signal level, the synthesized signal has the fifth signal level, and

the first and fourth signal levels are a low level, the second and fifth signal level are a high level, and the third signal level is a middle level.

6. The driving apparatus of claim 1, wherein the first and second control signals are each transferred to the gate and data drivers through different signal lines.

7. The driving apparatus of claim 1, wherein the signal extracting unit comprises first and second signal extractors extracting the first and second control signals, respectively.

8. The driving apparatus of claim 7, wherein the first signal extractor comprises at least one PMOS transistor and a plurality of NMOS transistors, and a number of the NMOS transistors is greater than a number of the PMOS transistors.

9. The driving apparatus of claim 8, wherein the PMOS transistor and the NMOS transistors have output and input terminals connected in series to each other, and have control terminals connected to each other and that are supplied with the synthesized signal.

10. The driving apparatus of claim 7, wherein the second signal extractor comprises a plurality of PMOS transistors and at least one NMOS transistor, and wherein the number of the PMOS transistors is greater than that of the NMOS transistor.

11. The driving apparatus of claim 10, wherein the PMOS transistors and the NMOS transistors have output and input terminals connected in series to each other, and have control terminals connected to each other and supplied with the synthesized signal.

12. The driving apparatus of claim 7, wherein one of the first and second signal extractors comprises an inverter.

13. The driving apparatus of claim 10, wherein the first control signal is a scanning start signal and the second control signal is a horizontal synchronization start signal.

14. A driving apparatus, comprising:

a signal controller synthesizing at least three signals having two signal levels to output a synthesized signal having at least four signal levels; and

a signal extracting unit extracting the at least three signals from the synthesized signal.

15. The driving apparatus of claim 14, wherein the signal extracting unit comprises a plurality of PMOS transistors and a plurality of NMOS transistors.

16. The driving apparatus of claim 14, further comprising a data driver and a gate driver outputting the data voltages and gate signals based on the three signals from the signal extracting unit, respectively.

17. A display device, comprising:

a signal controller synthesizing first and second signals, respectively, having first and second signal levels to output a synthesized signal having third to fifth signal levels;

a signal extracting unit extracting the first and second control signals from the synthesized signal;

a gate driver generating gate signals based on the first control signal; and

a data driver generating data signals based on the second control signal.

18. The display device of claim 17, wherein the first control signal is a scanning start signal and the second control signal is a horizontal synchronization start signal.

19. A driving method of a display device, comprising:

synthesizing first and second control signals of two signal levels to output a synthesized signal having three signal levels;

extracting the first and second control signals from the synthesized signal;

outputting gate signals based on the extracted first control signal; and

outputting data signals based on the extracted second control signal.