Multiple processor system and method including multiple memory hub modules
First Claim
1. A memory hub for use in coupling each of a plurality of memory requesters to each of a plurality of memory devices, the memory hub, comprising:
- a plurality of memory controllers, each of the memory controllers being coupled to at least one of the memory devices;
a first plurality of link interfaces; and
a cross bar switch having a first plurality of switch ports and a plurality of memory ports, each of the switch ports being coupled to a respective one of the link interfaces, and each of the memory ports being coupled to a respective one of the memory controllers, the cross bar switch being operable to selectively couple each of the link interfaces to any one of the memory controllers.
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Accused Products
Abstract
A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly accessed by any of several processors, and the memory modules in the second rank are accessed by the processors through the memory modules in the first rank. The data bandwidth between the processors and the memory modules in the second rank is varied by varying the number of memory modules in the first rank that are used to access the memory module in the second set. Each of the memory modules includes several memory devices coupled to a memory hub. The memory hub includes a memory controller coupled to each memory device, a link interface coupled to a respective processor or memory module, and a cross bar switch coupling any of the memory controllers to any of the link interfaces.
138 Citations
2 Claims
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1. A memory hub for use in coupling each of a plurality of memory requesters to each of a plurality of memory devices, the memory hub, comprising:
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a plurality of memory controllers, each of the memory controllers being coupled to at least one of the memory devices;
a first plurality of link interfaces; and
a cross bar switch having a first plurality of switch ports and a plurality of memory ports, each of the switch ports being coupled to a respective one of the link interfaces, and each of the memory ports being coupled to a respective one of the memory controllers, the cross bar switch being operable to selectively couple each of the link interfaces to any one of the memory controllers.
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2-45. -45. (canceled)
Specification