Memory hub and method for memory sequencing
First Claim
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1. A memory module, comprising:
- a plurality of memory devices; and
a memory hub, comprising;
a link interface receiving memory requests for access to memory cells in at least one of the memory devices;
a memory device interface coupled to the memory devices, the memory device interface being operable to couple memory requests to the memory devices for access to memory cells in at least one of the memory devices and to receive read data responsive to at least some of the memory requests;
a performance counter coupled to the memory device interface, the performance counter operable to track at least one performance metric; and
a memory sequencer coupled to the link interface and the memory device interface, the memory sequencer being operable to couple memory requests to the memory device interface responsive to memory requests received from the link interface, the memory sequencer further being operable to dynamically adjust operability responsive to the performance metric tracked by the performance counter.
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Abstract
A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics—for example, page hit rate, prefetch hits, and/or cache hit rate. The performance counter communicates with a memory sequencer that adjusts its operation based on the system metrics tracked by the performance counter.
138 Citations
2 Claims
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1. A memory module, comprising:
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a plurality of memory devices; and
a memory hub, comprising;
a link interface receiving memory requests for access to memory cells in at least one of the memory devices;
a memory device interface coupled to the memory devices, the memory device interface being operable to couple memory requests to the memory devices for access to memory cells in at least one of the memory devices and to receive read data responsive to at least some of the memory requests;
a performance counter coupled to the memory device interface, the performance counter operable to track at least one performance metric; and
a memory sequencer coupled to the link interface and the memory device interface, the memory sequencer being operable to couple memory requests to the memory device interface responsive to memory requests received from the link interface, the memory sequencer further being operable to dynamically adjust operability responsive to the performance metric tracked by the performance counter.
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2-38. -38. (canceled)
Specification
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Current AssigneeRound Rock Research LLC
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Original AssigneeJoseph Jeddeloh
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InventorsJeddeloh, Joseph
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Granted Patent
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Time in Patent OfficeDays
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Field of Search
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US Class Current711/154
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CPC Class CodesG06F 12/0215 with look ahead addressing ...G06F 12/0862 with prefetchG06F 12/0888 using selective caching, e....G06F 2212/6022 Using a prefetch buffer or ...G06F 2212/6026 Prefetching based on access...
