Reconfigurable integrated circuit device

• US 20070033369A1
• Filed: 01/27/2006
• Published: 02/08/2007
• Est. Priority Date: 08/02/2005
• Status: Abandoned Application

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Limited
• Inventors: Kasama, Ichiro, Nishida, Masaru, Tsuruta, Toru
• Application Number:
  US11/340,871
• Publication Number:
  US 20070033369A1
• Time in Patent Office: Days
• US Class Current: 711/170
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors

Abstract

A reconfigurable integrated circuit device which is dynamically constructed to be an arbitrary operation status based on a configuration data, has a plurality of clusters including operation processor elements, a memory processor element, and an inter-processor element switch group for connecting the elements in an arbitrary status; an inter-cluster switch group for constructing data paths between the clusters in an arbitrary status; and an external memory bus. A direct memory access control section, for executing the data transfer between the memory processor element and the external memory by direct memory access responding to an access request from the memory processor elements of the plurality of clusters, is further provided.

Claims

1. A reconfigurable integrated circuit device which is dynamically configured to be in arbitrary operation status based on a configuration data, comprising:

a plurality of clusters further including a plurality of operation processor elements having a computing unit respectively, a memory processor element having a memory to perform data transfer with an external memory, and an inter-processor element switch group for connecting the operation processor elements and the memory processor element in an arbitrary status;

an inter-cluster switch group for configuring data paths between the clusters in an arbitrary status; and

an external memory bus for performing data transfer between the memory processor element and the external memory, wherein

the operation processor elements, the memory processor element, the inter-processor element switch group and the inter-cluster switch group are dynamically changed based on the configuration data, and the device further comprising;

a direct memory access control section for executing data transfer between the memory processor element and the external memory by direct memory access responding to an access request from the memory processor elements of the plurality of clusters.

2. The reconfigurable integrated circuit device according to claim 1, wherein the cluster further comprises a configuration data memory for storing the configuration data, and a sequencer for outputting configuration data to configure the next operation status from the configuration data memory responding to an end signal from the operation processor element and memory processor element.

3. The reconfigurable integrated circuit device according to claim 1, further comprising a data flow control section which is installed as a common for the plurality of memory processor elements for accepting direct memory access requests from the plurality of memory processor elements, and instructing synchronized direct memory access requests to the direct memory access control section for the plurality of memory processor elements.

4. The reconfigurable integrated circuit device according to claim 1, further comprising a data flow control section which is installed as a common for the plurality of memory processor elements for accepting a direct memory access request from the plurality of memory processor elements and instructing synchronized direct memory access requests to the direct memory access control section for the plurality of memory processor elements, wherein

when a direct memory access request is accepted from a single memory processor element, the data flow control section instructs the direct memory access request to the direct memory access control section responding to the acceptance.

5. The reconfigurable integrated circuit device according to claim 1, wherein

the memory processor element further comprises an internal side interface with an internal bus which is connected to the inter-processor element switch group, and an external interface with the external memory bus, and wherein

the operation processor element accesses the memory processor element via the internal side interface while the memory processor element is accessing the external memory, by direct memory access, via the external side interface.

6. The reconfigurable integrated circuit device according to claim 5, wherein

the memory processor element further comprises first and second memory banks, and wherein

the first and second memory banks are alternately connected to the internal side and external side interfaces based on the configuration data.

7. The reconfigurable integrated circuit device according to claim 6, wherein

the memory processor element allows for data transfer between the operation processor element and the first or second memory bank after data transfer between the external memory and the first or second bank completes, and

if the data transfer between the external memory and the first or second memory banks does not complete, the memory processor element asserts a stall signal to instruct to stop operation to the plurality of operation processor elements, and negates the stall signal when data transfer between the external memory and the first or second memory bank completes.

8. The reconfigurable integrated circuit device according to claim 3, wherein the memory processor element monitors the operation status of the direct memory access control section, and supplies the access request to the data flow control section based on the operation status.

9. The reconfigurable integrated circuit device according to claim 8, wherein the memory processor element variably controls the timing of the access request based on the operation status.

10. The reconfigurable integrated circuit device according to claim 1, wherein the memory processor element accepts data transfer with the operation processor element while performing data transfer with the external memory by direct memory access, asserts a stall signal to stop the operation of the plurality of operation processor elements when the data transfer by the direct memory access cannot follow up the data transfer with the operation processor element, and negates the stall signal when follow up is possible.

11. The reconfigurable integrated circuit device according to claim 5, wherein the external interface of the memory processor element is constructed in an interface status corresponding to the plurality of data bus widths based on the configuration data.

12. The reconfigurable integrated circuit device according to claim 1, wherein

the memory processor element further comprises first and second memory banks, and

the memory processor element sets one of the first and second memory banks to a status for enabling access to the external bus side at startup based on the configuration data, and outputting the access request.

13. The reconfigurable integrated circuit device according to claim 12, wherein the memory processor element asserts an operation execution enable signal to the operation processor element when one of the first and second memory banks completes the data transfer by the direct memory access, to prompt the operation processor element to execute operation.

14. The reconfigurable integrated circuit device according to claim 13, wherein the memory processor element asserts a stall signal to request an operation stop of the operation processor element when both of the first and second memory banks enter data transfer disable status.

15. The reconfigurable integrated circuit device according to claim 13, wherein the cluster further comprises a plurality of memory processor elements and comprises an operation execution control section in common with the memory processor elements for requesting synchronized operation execution to the plurality of operation processor elements responding to the assert of an operation execution enable signal from the plurality of memory processor elements.

16. A reconfigurable integrated circuit device which is dynamically configured to be a predetermined operation status based on a configuration data, comprising:

a plurality of clusters including an operation processor element having a computing unit, a memory processor element having a memory to perform data transfer with an external memory, and an inter-processor element switch group for connecting the operation processor element and the memory processor element in an arbitrary status;

an inter-cluster switch group for configuring data paths between the clusters in an arbitrary status; and

an external memory bus for performing data transfer between the memory processor element and the external memory, wherein

the operation processor element, the memory processor element, the inter-processor element switch group and the inter-cluster switch group are dynamically changed based on the configuration data, and the device further comprising;

a direct memory access control section for executing data transfer between the memory processor element and external memory by direct memory access responding to the access requests from the memory processor elements of the plurality of clusters, wherein

the memory processor element includes first and second memory banks, wherein while one of the first and second memory banks is performing data transfer with the external memory by direct memory access, the other of the first and second memory banks performs data transfer with the operation processor element.