Delay distribution calculation method, circuit evaluation method and false path extraction method

• US 20070033554A1
• Filed: 10/05/2006
• Published: 02/08/2007
• Est. Priority Date: 11/22/2000
• Status: Abandoned Application

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Tanaka, Masakazu, Fukui, Masahiro, Tsukiyama, Shuji
• Application Number:
  US11/543,224
• Publication Number:
  US 20070033554A1
• Time in Patent Office: Days
• US Class Current: 716/108
• CPC Class Codes: G05B 19/0421 Multiprocessor system
• CPC Class Codes: G06F 2111/08 Probabilistic or stochastic CAD
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/00 Computer-aided design [CAD]
• CPC Class Codes: G06F 30/3312 Timing analysis
• CPC Class Codes: G06F 30/3315 using static timing analysis [STA]

Abstract

Delay distribution in an integrated circuit is calculated while taking into account a correlation of performance between interconnects or elements in the integrated circuit, thereby improving estimation accuracy. Circuit information, performance distribution information of the interconnects or elements in the integrated circuit, and correlation information of performance between the interconnects or elements are input. A vertex is selected for calculation, and a correlation between delay distribution at the selected vertex and delay distribution in a partial circuit including the selected vertex is calculated based on the performance distribution information and the correlation information.

Claims

1-15. -15. (canceled)

16. A method for extracting a false path in an integrated circuit to be designed, wherein the false path is extracted using an activating condition of a non-control signal edge within each logic gate included in the integrated circuit.

17. The method according to claim 16, comprising the steps of:

propagating a logic value listed in the activating condition of a non-control signal edge within a first gate by a propagation process;

conducting repeatedly the propagation step while the value to be propagated is a control signal; and

detecting a path from the first gate to a second gate as the false path when the propagated value is inconsistent with the activating condition of a non-control signal edge within the second gate.