Clock tree adjustable buffer
First Claim
1. An adjustable buffer, comprising:
- a first plurality of P-channel devices having current electrodes coupled in series between a first voltage supply and a first output node and having a corresponding first plurality of control electrodes, wherein each of said first plurality of control electrodes is coupled to a selected one of an input node and a second voltage supply collectively forming a first plurality of selectable connections; and
a first plurality of N-channel devices having current paths coupled in series between said first output node and said second voltage supply and having a corresponding second plurality of control electrodes, wherein each of said second plurality of control electrodes is coupled to a selected one of said input node and said first voltage supply collectively forming a second plurality of selectable connections;
wherein said first and second plurality of selectable connections are made to adjust delay from said input node to said first output node.
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Abstract
An adjustable buffer including a first series of P-channel devices having current electrodes coupled in series between a first voltage supply and a first output node, and a first series of N-channel devices having current electrodes coupled in series between the first output node and a second voltage supply. The control electrodes of the P- and N-channel devices are coupled to a selected one of an input node and a corresponding voltage supply collectively forming first and second sets of selectable connections. The first and second sets of selectable connections are made to adjust delay from the input node to the first output node. A clock distribution system including multiple uniform adjustable buffers coupled between at least one root node and multiple destination nodes, where each uniform adjustable buffer is adjustable between a minimum delay and a maximum delay.
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Citations
20 Claims
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1. An adjustable buffer, comprising:
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a first plurality of P-channel devices having current electrodes coupled in series between a first voltage supply and a first output node and having a corresponding first plurality of control electrodes, wherein each of said first plurality of control electrodes is coupled to a selected one of an input node and a second voltage supply collectively forming a first plurality of selectable connections; and
a first plurality of N-channel devices having current paths coupled in series between said first output node and said second voltage supply and having a corresponding second plurality of control electrodes, wherein each of said second plurality of control electrodes is coupled to a selected one of said input node and said first voltage supply collectively forming a second plurality of selectable connections;
wherein said first and second plurality of selectable connections are made to adjust delay from said input node to said first output node. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A clock distribution system, comprising:
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a plurality of uniform adjustable buffers coupled between at least one root node and a plurality of destination nodes, wherein each of said plurality of uniform adjustable buffers is adjustable between a minimum delay and a maximum delay;
a first branch comprising a first set of said plurality of uniform adjustable buffers coupled in series between said at least one root node and a first destination node; and
a second branch comprising a second set of said plurality of uniform adjustable buffers coupled in series between said at least one root node and a second destination node;
wherein each of said plurality of uniform adjustable buffers of said first set is programmed with said minimum delay and wherein at least one of said plurality of uniform adjustable buffers of said second set is programmed with a larger delay than said minimum delay. - View Dependent Claims (10, 11, 12, 13)
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14. A method of distributing a clock signal for a circuit, comprising:
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distributing a first plurality of adjustable buffers from a first root node to a plurality of first destination nodes forming a plurality of first branches of a first clock tree;
determining a delay of each of the plurality of first branches assuming a predetermined minimum delay for each adjustable buffer and determining a slowest branch of the first clock tree; and
adjusting at least one adjustable buffer of each of the plurality of first branches other than the slowest branch to minimize delay differential between the plurality of first branches. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification