Situation sensitive memory performance

• US 20070033581A1
• Filed: 08/02/2005
• Published: 02/08/2007
• Est. Priority Date: 08/02/2005
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Gonzalez, Carlos, Tomlin, Andrew
• Granted Patent: US 7,502,921 B2
• Time in Patent Office: Days
• US Class Current: 717/154
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present invention presents a non-volatile memory system that adapts its performance to one or more system related situation. If a situation occurs where the memory will require more than the allotted time for completing an operation, the memory can switch from its normal operating mode to a high performance mode in order to complete the operation quickly enough. Conversely, if a situation arises where reliability could be an issue (such as partial page programming), the controller could switch to a high reliability mode. In either case, once the trigging system situation has returned to normal, the memory reverts to the normal operation. The detection of such situations can be used both for programming and data relocation operations. An exemplary embodiment is based on firmware programmable performance.

Claims

1. A memory system, comprising:

a memory having a rewritable data storage portion; and

a controller for managing data stored in the memory and controlling the transfer of data between the memory system and a host to which it is connected, wherein the controller operates the memory normally at a first performance level and operates the memory at a second, different performance level in response to a system related situation.

2. The memory system of claim 1, wherein the second performance level is of higher performance than the first performance level.

3. The memory system of claim 2, wherein the controller operates the memory at the second performance level in response to a high latency situation.

4. The memory system of claim 3, wherein said high latency situation is an error during programming.

5. The memory system of claim 3, wherein said high latency situation is an error during a data relocation operation.

6. The memory system of claim 3, wherein said high latency situation is a garbage collection operation.

7. The memory system of claim 2, wherein the second performance level uses a lower level of error detection and correction than the first performance level.

8. The memory system of claim 2, wherein the second performance level uses a faster programming sequence than the first performance level.

9. The memory system of claim 8, wherein the second performance level uses a faster clock speed than the first performance level.

10. The memory system of claim 9, wherein the second performance level uses programming pulses of longer duration than the first performance level.

11. The memory system of claim 9, wherein the second performance level uses programming pulses of greater amplitude than the first performance level.

12. The memory system of claim 2, wherein the controller additionally operates the memory at a third performance level in response to an additional system related situation, wherein the third performance level is of greater reliability than the first performance level.

13. The memory system of claim 1, wherein the second performance level is of greater reliability than the first performance level.

14. The memory system of claims 1, wherein the system related situation is partial page programming.

15. The memory system of claims 1, wherein the system related situation is a low voltage condition.

16. The memory system of claim 1, wherein the second performance level utilizes a higher degree of error detection and correction than the first performance level.

17. The memory system of claim 1, wherein the second performance level utilizes a slower programming sequence than the first performance level.

18. The memory system of claim 17, wherein the second performance level utilizes a slower clock rate than the first performance level.

19. The memory system of claim 17, wherein the second performance level utilizes programming pulses of shorter duration than the first performance level.

20. The memory system of claim 17, wherein the second performance level uses programming pulses of lesser amplitude.

21. A method of operating a memory system comprising a memory having a rewritable data storage portion and a controller for managing data stored in the memory and controlling the transfer of data between the memory system and a host to which the memory system is connected, the method comprising:

operating the memory at a first performance level;

determining by the controller of a system related situation; and

in response to said determining a system related situation, operating the memory a second performance level that differs from the first performance level.

22. The method of claim 21, wherein the second performance level is of higher performance than the first performance level.

23. The method of claim 22, wherein the controller operates the memory at the second performance level in response to a high latency situation.

24. The method of claim 23, wherein said high latency situation is an error during programming.

25. The method of claim 23, wherein said high latency situation is an error during a data relocation operation.

26. The method of claim 23, wherein said high latency situation is a garbage collection operation.

27. The method of claim 22, wherein the second performance level uses a lower level of error detection and correction than the first performance level.

28. The method of claim 22, wherein the second performance level uses a faster programming sequence than the first performance level.

29. The method of claim 28, wherein the second performance level uses a faster clock speed than the first performance level.

30. The method of claim 29, wherein the second performance level uses programming pulses of longer duration than the first performance level.

31. The method of claim 29, wherein the second performance level uses programming pulses of greater amplitude than the first performance level.

32. The method of claim 22, further comprising:

determining by the controller of an additional system related situation; and

in response to said determining a additional system related situation, operating the memory a third performance level in response to an additional system related situation, wherein the third performance level is of greater reliability than the first performance level.

33. The method of claim 21, wherein the second performance level is of greater reliability than the first performance level.

34. The memory system of claims 21, wherein the system related situation is partial page programming.

35. The memory system of claims 21, wherein the system related situation is a low voltage condition.

36. The memory system of claims 21, wherein the second performance level utilizes a higher degree of error detection and correction than the first performance level.

37. The memory system of claims 21, wherein the second performance level utilizes a slower programming sequence than the first performance level.

38. The method of claim 37, wherein the second performance level utilizes a slower clock rate than the first performance level.

39. The method of claim 37, wherein the second performance level utilizes programming pulses of shorter duration than the first performance level.

40. The method of claim 37 wherein the second performance level uses programming pulses of lesser amplitude.