MOS semiconductor device

• US 20070034940A1
• Filed: 08/10/2006
• Published: 02/15/2007
• Est. Priority Date: 08/12/2005
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Sanuki, Tomoya
• Application Number:
  US11/501,917
• Publication Number:
  US 20070034940A1
• Time in Patent Office: Days
• US Class Current: 257/327
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

A semiconductor device comprises a gate electrode provided on a gate insulating film, a side wall insulating film provided on a side wall of the gate electrode through a protection insulating film, a barrier SiN film provided to cover the gate electrode and the side wall insulating film, an inter-level insulating film provided to cover the barrier SiN film, and an SOG-series high-stress material being used as part of the inter-level insulating film.

Claims

1. A MOS semiconductor device comprising:

a gate electrode provided via a gate insulating film,

a side wall insulating film formed on a side wall of the gate electrode with a protection insulating film disposed therebetween,

a barrier SiN film formed to cover the gate electrode and side wall insulating film, and

an inter-level insulating film formed to cover the barrier SiN film,

wherein an SOG-series high-stress material is used as part of the inter-level insulating film.

2. The MOS semiconductor device according to claim 1, wherein the high-stress material is a PSZ (polysilazane) film.

3. The MOS semiconductor device according to claim 2, wherein the inter-level insulating film is formed to further cover the PSZ film and includes an insulating film which applies no stress to the MOS transistor.

4. The MOS semiconductor device according to claim 3, wherein the insulating film which applies no stress to the MOS transistor is a silicon oxide film.

5. The MOS semiconductor device according to claim 1, wherein the side wall insulating film is formed on a stress alleviating film which is formed on the semiconductor substrate.

6. The MOS semiconductor device according to claim 5, wherein the stress alleviating film is formed of TEOS which is an SiO₂-series material.

7. The MOS semiconductor device according to claim 1, wherein a CMOS semiconductor device includes an N-type MOS transistor and a P-type MOS transistor.

8. The MOS semiconductor device according to claim 1, wherein the MOS semiconductor device according to claim 1 is an N-type MOS transistor.

9. A MOS semiconductor device comprising:

a gate electrode provided via a gate insulating film,

a side wall insulating film directly formed on a side wall of the gate electrode, and

a barrier SiN film formed to cover the gate electrode and side wall insulating film,

wherein a material whose volume contracts is used as the side wall insulating film.

10. The MOS semiconductor device according to claim 9, wherein the material whose volume contracts is an SOG-series material.

11. The MOS semiconductor device according to claim 9, wherein the MOS semiconductor device is an N-type MOS transistor.

12. A gate structure of a MOS semiconductor device comprising:

a semiconductor substrate, and

N-type and P-type MOS transistors formed on the semiconductor substrate and isolated by an STI region,

wherein each of the N-type and P-type MOS transistors includes a gate electrode provided via a gate insulating film, a side wall insulating film formed on a side wall of the gate electrode with a protection insulating film disposed therebetween, a barrier SiN film formed to cover the gate electrode and side wall insulating film, and an inter-level insulating film formed to cover the barrier SiN film and an SOG-series high-stress material is used as part of the inter-level insulating film in the N-type MOS transistor.

13. The gate structure of the MOS semiconductor device according to claim 12, wherein the high-stress material is a PSZ (polysilazane) film.

14. The gate structure of the MOS semiconductor device according to claim 12, wherein the inter-level insulating film is formed to further cover the PSZ film and includes an insulating film which applies no stress to the N-type MOS transistor.

15. The gate structure of the MOS semiconductor device according to claim 14, wherein the insulating film which applies no stress to the N-type MOS transistor is a silicon oxide film.

16. The gate structure of the MOS semiconductor device according to claim 12, wherein the side wall insulating film is formed on a stress alleviating film which is formed on the semiconductor substrate in the P-type MOS transistor.

17. The gate structure of the MOS semiconductor device according to claim 12, wherein the barrier SiN film which covers the gate electrode of the N-type MOS transistor is removed from the upper surface of the gate electrode.