Nonvolatile semiconductor integrated circuit devices and fabrication methods thereof

• US 20070034955A1
• Filed: 07/17/2006
• Published: 02/15/2007
• Est. Priority Date: 08/09/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Tae-kyung, Choi, Jeong-hyuk
• Granted Patent: US 7,714,378 B2
• Time in Patent Office: Days
• US Class Current: 257/349
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

In a method for manufacturing a semiconductor device, an oxide layer, a first polysilicon layer, and a second polysilicon layer are sequentially provided on a substrate. A first hard mask pattern is provided on the second polysilicon layer. The oxide layer, the first polysilicon layer, and the second polysilicon layer are patterned using the first hard mask pattern as a mask to form a lower gate structure including an oxide pattern, a first polysilicon pattern, and a second polysilicon pattern. The lower gate structure is etched to provide an oxidation layer on sidewalls of the lower gate structure. An insulating layer is provided on the lower gate structure including the oxidation layer. The first hard mask pattern is removed to form a first opening in the insulating layer, the first opening exposing the second polysilicon pattern. A metal pattern is formed in the first opening on the second polysilicon pattern, the second polysilicon pattern having the oxidation layer on sidewalls thereof.

Claims

1. A method for manufacturing a semiconductor device, comprising:

sequentially providing an oxide layer, a first polysilicon layer, and a second polysilicon layer on a substrate;

providing a first hard mask pattern on the second polysilicon layer;

patterning the oxide layer, the first polysilicon layer, and the second polysilicon layer using the first hard mask pattern as a mask to form a lower gate structure including an oxide pattern, a first polysilicon pattern, and a second polysilicon pattern;

oxidizing the lower gate structure to provide an oxidation layer on sidewalls of the lower gate structure;

providing an insulating layer on the lower gate structure including the oxidation layer;

removing the first hard mask pattern to form a first opening in the insulating layer, the first opening exposing the second polysilicon pattern; and

forming a metal pattern in the first opening on the second polysilicon pattern, the second polysilicon pattern having the oxidation layer on sidewalls thereof.

2. The method of claim 1 wherein the metal pattern partially fills the first opening and further comprising:

enlarging a remaining upper portion of the first opening to form an enlarged first opening; and

forming a second hard mask pattern in the first opening on the metal pattern.

3. The method of claim 2 further comprising:

forming a second opening in the insulating layer by etching the insulating layer using the second hard mask pattern as an etch mask, the second opening exposing a portion of the substrate; and

filling the second opening with a conductive material to form an inter-layer contact.

4. The method of claim 3 wherein an upper portion of the inter-layer contact has a width that is greater than a lower portion of the inter-layer contact, and wherein the upper portion of the inter-layer contact overlaps a portion of the metal pattern.

5. The method of claim 4 further comprising connecting metal patterns of alternate gate structures to form transistor selection lines of a non-volatile memory device.

6. The method of claim 4 wherein the upper portion of the interlayer contact further overlaps an isolation region in the substrate adjacent the lower gate structure.

7. The method of claim 2 further comprising providing an inter-gate dielectric layer between the first polysilicon layer and the second polysilicon layer, and wherein patterning further comprises patterning the inter-gate dielectric layer to form an inter-gate dielectric pattern.

8. The method of claim 7 wherein the first polysilicon pattern comprises a floating gate, and wherein the second polysilicon pattern and the metal pattern comprise a control gate, of a non-volatile semiconductor device.

9. The method of claim 7 wherein the inter-gate dielectric layer comprises an oxide/nitride/oxide (ONO) layer.

10. The method of claim 7 further comprising forming a barrier layer pattern between the metal pattern and the second polysilicon layer pattern.

11. The method of claim 10 further comprising enlarging the first opening prior to forming the metal pattern to form an enlarged first opening and wherein the metal pattern is formed in the enlarged first opening.

12. The method of claim 11 wherein the metal pattern partially fills the enlarged first opening and further comprising:

further enlarging a remaining upper portion of the enlarged first opening to form a further enlarged first opening; and

forming a second hard mask pattern in the further enlarged first opening on the metal pattern.

13. The method of claim 1 wherein oxidizing the lower gate structure comprises heating the lower gate structure and immersing the structure in an atmosphere including oxygen,

14. The method of claim 1 wherein providing the oxide layer comprises forming the oxide layer at a first thickness in a first region of the substrate, and forming the oxide layer at a second thickness at a second region of the substrate, wherein the first thickness and the second thickness are different.

15. The method of claim 14 wherein semiconductor devices formed in the first region are field effect transistors and wherein semiconductor devices formed in the second region are floating gate transistors, and wherein the second thickness is greater than the first thickness.

16. The method of claim 1 further comprising connecting metal patterns of adjacent gate structures to form one of word lines and bit lines of a semiconductor device.

17. A method for manufacturing a semiconductor device, comprising:

sequentially providing a tunnel oxide layer, a floating gate polysilicon layer, an inter-gate dielectric layer and a control gate polysilicon layer on a substrate;

providing a first hard mask pattern on the control gate polysilicon layer;

patterning the tunnel oxide layer, the floating gate polysilicon layer, the inter-gate dielectric layer and the control gate polysilicon layer using the first hard mask pattern as a mask to form a lower gate structure including a tunnel oxide pattern, a floating gate polysilicon pattern, an inter-gate dielectric pattern and a control gate polysilicon pattern;

oxidizing the lower gate structure to provide an oxidation layer on sidewalls of the lower gate structure;

providing an insulating layer on the lower gate structure including the oxidation layer;

removing the first hard mask pattern to form a first opening in the insulating layer, the first opening exposing the control gate polysilicon pattern; and

forming a metal pattern in the first opening on the control gate polysilicon pattern, the control gate polysilicon pattern having the oxidation layer on sidewalls thereof.

18. The method of claim 17 wherein the inter-gate dielectric layer comprises an oxide/nitride/oxide (ONO) layer.

19. The method of claim 17 wherein oxidizing the lower gate structure comprises heating the lower gate structure and immersing the structure in an atmosphere including oxygen,

20. The method of claim 17 wherein the metal pattern partially fills the first opening and further comprising:

enlarging a remaining upper portion of the first opening to form an enlarged first opening; and

forming a second hard mask pattern in the first opening on the metal pattern.

21. The method of claim 20 further comprising:

forming a second opening in the insulating layer by etching the insulating layer using the second hard mask pattern as an etch mask, the second opening exposing a portion of the substrate; and

filling the second opening with a conductive material to form an inter-layer contact.

22. The method of claim 21 wherein an upper portion of the inter-layer contact has a width that is greater than a lower portion of the inter-layer contact, and wherein the upper portion of the inter-layer contact overlaps a portion of the metal pattern.

23. The method of claim 22 further comprising connecting metal patterns of alternate gate structures to form transistor selection lines of a non-volatile memory device.

24. The method of claim 22 wherein the upper portion of the interlayer contact further overlaps an isolation region in the substrate adjacent the lower gate structure.

25. The method of claim 17 further comprising forming a barrier layer pattern between the metal pattern and the control gate polysilicon layer pattern.

26. The method of claim 25 further comprising enlarging the first opening prior to forming the metal pattern to form an enlarged first opening and wherein the metal pattern is formed in the enlarged first opening.

27. The method of claim 26 wherein the metal pattern partially fills the enlarged first opening and further comprising:

further enlarging a remaining upper portion of the enlarged first opening to form a further enlarged first opening; and

forming a second hard mask pattern in the further enlarged first opening on the metal pattern.

28. The method of claim 17 wherein providing the oxide layer comprises forming the oxide layer at a first thickness in a first region of the substrate, and forming the oxide layer at a second thickness at a second region of the substrate, wherein the first thickness and the second thickness are different.

29. The method of claim 28 wherein semiconductor devices formed in the first region are field effect transistors and wherein semiconductor devices formed in the second region are floating gate transistors, and wherein the second thickness is greater than the first thickness.

30. The method of claim 17 further comprising connecting metal patterns of adjacent gate structures to form one of word lines and bit lines of a semiconductor device.

31. A semiconductor device comprising:

a semiconductor substrate;

a tunnel oxide layer pattern on the substrate;

a floating gate polysilicon layer pattern on the tunnel oxide layer pattern;

an inter-gate dielectric layer pattern on the floating gate polysilicon layer pattern;

a control gate polysilicon layer pattern on the inter-gate dielectric layer pattern;

a control gate metal layer pattern on the control gate polysilicon layer pattern, wherein a width of the control gate metal layer pattern is greater than a width of the control gate polysilicon layer pattern.

32. The semiconductor device of claim 31 wherein the tunnel oxide layer pattern, the floating gate polysilicon layer pattern, the inter-gate dielectric layer pattern, the control gate polysilicon layer pattern and the control gate metal layer pattern comprise a floating gate structure and wherein the floating gate structure is on an active region of the semiconductor substrate, and wherein source and drain regions are in the semiconductor substrate adjacent sidewalls of the floating gate structure.

33. The semiconductor device of claim 31 wherein multiple floating gate structures are provided on the semiconductor substrate and further comprising an insulating layer on the substrate and on the multiple floating gate structures, and further comprising an inter-layer contact in the insulting layer between a pair of the multiple floating gate structures.

34. The semiconductor device of claim 33 wherein the inter-layer contact has an upper portion that is wider than a lower portion thereof, and wherein the upper portion of the inter-layer contact overlaps a portion of the control gate metal layer pattern.

35. The semiconductor device of claim 33 wherein the control gate metal layer patterns of adjacent floating gate structures are connected to provide one of word lines and bit lines of the semiconductor device.

36. The semiconductor device of claim 33 further comprising a hard mask pattern on the control gate metal layer pattern, wherein a width of the hard mask pattern is greater than a width of the control gate metal layer pattern, and wherein the hard mask pattern is used for self-alignment of the inter-layer contact.

37. A semiconductor device comprising:

a semiconductor substrate;

multiple gate structures, each comprising;

a tunnel oxide layer pattern on the substrate;

a first polysilicon layer pattern on the tunnel oxide layer pattern;

a second polysilicon layer pattern on the first polysilicon layer pattern;

a metal layer pattern on the second polysilicon layer pattern; and

a hard mask pattern on the metal layer pattern, wherein a width of the hard mask pattern is greater than a width of the metal layer pattern;

an insulating layer on the substrate and on the multiple gate structures; and

an inter-layer contact in the insulting layer between a pair of the multiple gate structures, wherein the hard mask pattern is used for self-alignment of the inter-layer contact.

38. The semiconductor device of claim 37 wherein a width of the metal layer pattern is greater than a width of the second polysilicon layer pattern.

39. The semiconductor device of claim 37 wherein the first polysilicon layer pattern has a dopant concentration that is different than the second polysilicon layer pattern.

40. The semiconductor device of claim 37 further comprising an inter-gate dielectric layer pattern on the first polysilicon layer pattern, and wherein the semiconductor device comprises a floating gate device.

41. The semiconductor device of claim 37 wherein the semiconductor device comprises a field effect transistor.

42. The semiconductor device of claim 37 further comprising source and drain regions in the semiconductor substrate adjacent sidewalls of the gate structures.

43. The semiconductor device of claim 37 wherein the inter-layer contact has an upper portion that is wider than a lower portion thereof, and wherein the upper portion of the inter-layer contact overlaps a portion of the metal layer pattern.

44. The semiconductor device of claim 37 wherein the metal layer patterns of adjacent gate structures are connected to provide one of word lines, bit lines, and transistor selection lines of the semiconductor device.