Tri-gate devices and methods of fabrication

• US 20070034972A1
• Filed: 10/25/2006
• Published: 02/15/2007
• Est. Priority Date: 08/23/2002
• Status: Active Grant

• Current Assignee: Brian J. Doyle, Douglas Barlage, Jack Kavalieros, Robert Chau, Suman Datta
• Original Assignee: Brian J. Doyle, Douglas Barlage, Jack Kavalieros, Robert Chau, Suman Datta
• Inventors: Kavalieros, Jack, Datta, Suman, Chau, Robert, Doyle, Brian, Barlage, Douglas
• Granted Patent: US 7,560,756 B2
• Time in Patent Office: Days
• US Class Current: 257/401
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/772 Field effect transistors
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7854 with rounded corners
• CPC Class Codes: H01L 29/78645 with multiple gate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10K 10/482 the IGFET comprising multiple separately-addressable gate electrodes
• CPC Class Codes: H10K 85/221 Carbon nanotubes
• CPC Class Codes: Y10S 977/742 Carbon nanotubes, CNTs
• CPC Class Codes: Y10S 977/842 for carbon nanotubes or fullerenes
• CPC Class Codes: Y10S 977/938 Field effect transistors, FETS, with nanowire- or nanotube-channel region

Abstract

The present invention is a semiconductor device comprising a carbon nanotube body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the carbon nanotube body and on the laterally opposite sidewalls of the carbon nanotube body. A gate electrode is formed on the gate dielectric on the top surface of the carbon nanotube body and adjacent to the gate dielectric on the laterally opposite sidewalls of the carbon nanotube body.

Claims

1. A semiconductor device comprising:

a carbon nanotube (CNT) body having a top surface and laterally opposite side surfaces formed on a substrate;

a gate dielectric formed on the top surface of the CNT body and on the laterally opposite side surfaces of the CNT body; and

a gate electrode formed on the gate dielectric on the top surface of the CNT body and adjacent to the gate dielectric on the laterally opposite side surfaces of the CNT body.

2. The semiconductor device of claim 1, wherein the substrate comprises an insulating substrate.

3. The semiconductor device of claim 1, wherein the substrate comprises a semiconductor substrate.

4. The semiconductor device of claim 1, wherein a distance between the laterally opposite side surfaces is approximately equal to a distance between the top surface of the CNT body and the substrate.

5. The semiconductor device of claim 1, wherein a height of the CNT body from the substrate to the top surface is between ½

and 2 times a distance between the laterally opposite side surface of the CNT body.

6. The semiconductor device of claim 1, further comprising a source region and a drain region formed in the CNT body, wherein the source region and the drain region are sited on opposite sides of the gate electrode, and wherein a channel region is formed in the CNT body between the source region and the drain region beneath the gate electrode.

7. The semiconductor device of claim 6, further comprising a halo region formed in the channel region of the CNT body.

8. A method of forming a semiconductor device comprising:

forming a CNT body having a top surface and laterally opposite side surfaces on a substrate;

forming a gate dielectric on the top surface of the CNT body and on the laterally opposite side surfaces of the CNT body; and

forming a gate electrode on the gate dielectric and adjacent to the gate dielectric on the laterally opposite side surfaces of the CNT body.

9. The method of claim 8, further comprising forming a source region and a drain region on the CNT body, wherein the source region is formed on one side of the gate electrode and the drain region is formed on the other side of the gate electrode, and wherein a portion of the CNT body beneath the gate electrode and between the source region and drain region comprises a channel region.

10. The method of claim 9, further comprising doping a portion of the channel region to form a halo region.