Chip-scale schottky device

• US 20070034984A1
• Filed: 10/18/2006
• Published: 02/15/2007
• Est. Priority Date: 11/06/2002
• Status: Active Grant

• Current Assignee: Siliconix Technology CV (Vishay Intertechnology Incorporated)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Skocki, Slawomir
• Granted Patent: US 8,921,969 B2
• Time in Patent Office: Days
• US Class Current: 257/484
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/06051 Bonding areas having different shapes
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/72 Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
• CPC Class Codes: H01L 29/417 carrying the current to be rectified, amplified or switched
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/12032 Schottky diode
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

A chip-scale schottky package which has at least one cathode electrode and at least one anode electrode disposed on only one major surface of a die, and solder bumps connected to the electrode for surface mounting of the package on a circuit board.

Claims

1. A semiconductor device comprising:

a semiconductor die having a first major surface;

a first electrode schottky coupled to a portion of said first major surface;

a second electrode electrically connected to said first major surface of said semiconductor die, but spaced from said first electrode; and

a guard diffusion formed in said semiconductor die in a region at least partly between said first electrode and said second electrode, wherein said semiconductor die includes a first lightly doped portion and a second highly doped portion, said first lightly doped portion being disposed over said second highly doped portion, and further comprising a sinker extending from a major surface of said first portion to said second portion, and wherein said second electrode is electrically connected to said sinker.

2. The device of claim 1, further comprising a passivation layer disposed over said first electrode and said second electrode, and a plurality of solder bumps disposed over a free surface of said passivation layer and extending through openings in said passivation layer to said first and second electrodes.

3. The device of claim 1, wherein said guard diffusion surrounds said first electrode.

4. The device of claim 3, wherein said first electrode surrounds said second electrode.

5. The device of claim 1, wherein said first electrode is schottky coupled through a schottky barrier.

6. The device package of claim 5, wherein said schottky barrier is comprised of molybdenum.

7. The device of claim 5, wherein said schottky barrier is comprised of palladium.

8. The device of claim 5, wherein said schottky barrier is comprised of vanadium.

9. The device of claim 1, wherein said first electrode and said second electrode are comprised of aluminum.

10. The device of claim 2, further comprising a layer of nickel disposed between at least one of said plurality of solder bumps and its associated electrode.

11. The device of claim 2, wherein said passivation layer comprises of silicon nitride.

12. The device of claim 1, wherein said semiconductor die includes a second major surface opposite to said first major surface, said second major surface being free of any electrical connection.

13. The device of claim 1, wherein said semiconductor die includes side edges which define lateral boundaries for said semiconductor device.

14. The device of claim 1, wherein said first electrode is an anode electrode and said second electrode is a cathode electrode.