Differential chip performance within a multi-chip package

• US 20070035007A1
• Filed: 08/15/2005
• Published: 02/15/2007
• Est. Priority Date: 08/15/2005
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Dietz, James, Negussu, Petros, Le, Thoai
• Granted Patent: US 7,518,231 B2
• Time in Patent Office: Days
• US Class Current: 257/700
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A multi-chip package comprises a first die comprising a first integrated circuit and a second die comprising a second integrated circuit. A first plurality of contact pads disposed on the first die are coupled to the first integrated circuit, wherein the first plurality of contact pads comprises a first mode pad coupled to a first device formed on the first die. The first mode pad is coupled to a first potential and causes the first device to operate in a first mode. A second plurality of contact pads disposed on the second die are coupled to the second integrated circuit. The second plurality of contact pads comprises a second mode pad coupled to a second device formed on the second die. The second mode pad is coupled to a second potential and causes the second device to operate in a second mode. The first mode and the second mode are selected based on the relative position of the first die and the second die.

Claims

1. A multi-chip package, comprising:

a die of the multi-chip package comprising an integrated circuit and a device; and

a plurality of contact pads disposed on the die and coupled to the integrated circuit;

wherein the plurality of contact pads comprises a mode pad disposed on the die, wherein the mode pad being placed at different potentials causes the device to operate in one of at least two modes, the mode being selected based on a position of the die in the multi-chip package relative to at least one other die in the multi-chip package.

2. The multi-chip package of claim 1, wherein the mode is selected to achieve a relatively more balanced performance of the integrated circuit relative to an integrated circuit of the at least one other die in the multi-chip package.

3. The multi-chip package of claim 1, wherein the device is a driver which drives an output signal for the integrated circuit, and wherein the driver comprises a normal and an additional driver, and wherein the default driver provides a regular drive strength for the output signal in a first mode and wherein the default driver and the additional driver cooperate to provide an increased drive strength for the signal in a second mode.

4. The multi-chip package of claim 1, wherein leaving the mode pad uncoupled causes the device to operate in a default mode, the default mode being one of the at least two modes.

5. A multi-chip package, comprising:

a first die of the multi-chip package comprising a first integrated circuit;

a first plurality of contact pads disposed on the first die and coupled to the first integrated circuit, wherein the first plurality of contact pads comprises a first mode pad coupled to a first device formed on the first die, wherein the first mode pad is coupled to a first potential and causes the first device to operate in a first mode;

a second die of the multi-chip package comprising a second integrated circuit;

a second plurality of contact pads disposed on the second die and coupled to the second integrated circuit, wherein the second plurality of contact pads comprises a second mode pad coupled to a second device formed on the second die, wherein the second mode pad is coupled to a second potential and causes the second device to operate in a second mode, the first mode and the second mode being selected based on the relative position of the first die and the second die.

6. The multi-chip package of claim 5 wherein the first mode and the second mode are selected to achieve a relatively more balanced performance of the first and second dies.

7. The multi-chip package of claim 5 wherein the first device and the second device are a same type of device.

8. The multi-chip package of claim 5, wherein the first device comprises a first driver, and wherein the first mode of the first driver provides regular drive strength for a signal being output by the first integrated circuit and wherein the second device comprises a second driver, and wherein the second mode of the second driver provides increased drive strength for a signal being output by the second first integrated circuit.

9. The multi-chip package of claim 5, wherein the first mode selects a first setup and hold time for a receiver on the first integrated circuit and wherein the second mode selects a second setup and hold time for a receiver on the second integrated circuit, the first and second setup and hold times being different.

10. A multi-chip package, comprising:

a substrate;

at least two dies disposed on the substrate, each die comprising a contact plurality of pads and a mode pad coupled to a device formed on the respective die, wherein the mode pad of at least one of the dies is coupled to a first potential causing the respective device to operate in a first mode and wherein the mode pad of at least one other die is coupled to a second potential causing the respective device to operate in a second mode, the mode being selected based on a relative position of the respective dies in the multi-chip package; and

wire bonds coupling the plurality of contract pads to contact elements of the substrate, thereby creating signal paths between the respective dies and the substrate.

11. The multi-chip package of claim 10, wherein the first mode and the second mode are selected to achieve a relatively more balanced performance of the dies.

12. The multi-chip package of claim 10, wherein the devices coupled to the mode pads are a same type of device.

13. The multi-chip package of claim 10, further comprising wire bonds coupling the mode pads to contact elements of the substrate.

14. The multi-chip package of claim 10, wherein the multi-chip package is disposed on a printed circuit board.

15. A multi-chip memory package, comprising:

a first die of a multi-chip package comprising a first memory circuit;

a first plurality of contact pads disposed on the first die and coupled to the first memory circuit, wherein the first plurality of contact pads comprises a first mode pad coupled to a first device formed on the first die, wherein the first mode pad is coupled to a first potential and causes the first device to operate in a first mode;

a second die of the multi-chip package comprising a second memory circuit;

a second plurality of contact pads disposed on the second die and coupled to the second memory circuit, wherein the second plurality of contact pads comprises a second mode pad coupled to a second device formed on the second die, wherein the second mode pad is coupled to a second potential and causes the second device to operate in a second mode, the first mode and the second mode being selected based on the relative position of the first die and the second die.

16. The multi-chip memory package of claim 15 wherein the first mode and the second mode are selected to achieve a relatively more balanced performance of the first and second dies.

17. The multi-chip memory package of claim 15, wherein the first device and the second device are a same type of device.

18. The multi-chip memory package of claim 15, wherein the first device is a first driver, and wherein the first mode of the first driver provides regular drive strength for a signal being output by the first integrated circuit and wherein the second device is a second driver, and wherein the second mode of the second driver provides increased drive strength for a signal being output by the second first integrated circuit.

19. The multi-chip memory package of claim 18, wherein the first driver comprises a first default driver and a first additional driver, and wherein the first default driver provides a regular drive strength for the first output signal, and wherein the second driver comprises a second default driver and a second additional driver, and wherein the second default driver provides a regular drive strength for the second output signal and the second additional driver provides an increased drive strength for the second output signal.

20. The multi-chip memory package of claim 15, wherein the first mode selects a first setup and hold time for a receiver on the first memory circuit and wherein the second mode selects a second setup and hold time for a receiver on the second memory circuit.

21. A method of packaging integrated circuits in a multi-chip package, the method comprising:

coupling a first plurality of contact pads disposed on a first die to a substrate, wherein the first die comprises a first integrated circuit coupled to the first plurality of contact pads and a first device coupled to a first mode selection pad;

coupling the first mode selection pad to a first potential on the substrate, wherein coupling the first mode selection pad to the first potential causes the first device to operate in a first mode;

coupling a second plurality of contact pads disposed on a second die to the substrate, wherein the second die comprises a second integrated circuit coupled to the second plurality of contact pads and a second device coupled to a second mode selection pad;

coupling the second mode selection pad to a second potential on the substrate, wherein coupling the second mode selection pad to the second potential causes the second device to operate in a second mode; and

selecting the first mode and the second mode based on the relative position of the first die and the second die.

22. A multi-chip package, comprising:

means for supporting circuitry;

means for housing a first integrated circuit, the means for housing the first integrated circuit disposed on the means for supporting, the means for housing the first integrated circuit comprising a means for connecting to the first integrated circuit and a means for selecting a mode of a first device formed on the means for housing the first integrated circuit, wherein the means for selecting the mode of the first device is connected to a first potential causing the first device to operate in a first mode;

means for housing a second integrated circuit, the means for housing the second integrated circuit disposed on the means for supporting, the means for housing the second integrated circuit comprising a means for connecting to the second integrated circuit and a means for selecting a mode of a second device formed on the means for housing the second integrated circuit, wherein the means for selecting the mode of the second device is connected to a second potential causing the second device to operate in a second mode;

the first and second mode being selected based on a relative position of the means for housing the first integrated circuit and the means for housing the second integrated circuit in the multi-chip package; and

means for coupling the means for connecting to the first integrated circuit and the means for connecting to the second integrated circuit to contact elements disposed on the means for supporting, thereby creating signal paths between the respective means for housing and the means for supporting.