Stackable tier structure comprising high density feedthrough

• US 20070035033A1
• Filed: 09/20/2006
• Published: 02/15/2007
• Est. Priority Date: 05/26/2005
• Status: Active Grant

• Current Assignee: Nytell Software LLC (Intellectual Ventures LLC)
• Original Assignee: Aprolase Development Co LLC (Intellectual Ventures LLC)
• Inventors: Ozguz, Volkan, Stern, Jonathan
• Granted Patent: US 7,919,844 B2
• Time in Patent Office: Days
• US Class Current: 257/777
• CPC Class Codes: H01L 21/4803 Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks H01L21/4846 takes precedence; printed circuit boards H05K1/00
• CPC Class Codes: H01L 21/4846 Leads on or in insulating or insulated substrates, e.g. metallisation H01L21/4821 takes precedence; metallisation of ceramics in general C04B41/51; printed circuits H05K3/00
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/24227 the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
• CPC Class Codes: H01L 2224/32188 the layer connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 2225/1035 the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/1094 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/3672 Foil-like cooling fins or heat sinks being part of lead-frames H01L23/49568
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/52 Arrangements for conducting electric current within the device in operation from one component to another , i.e. interconnections, e.g. wires, lead frames optical interconnections G02B6/00
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/07811 : Extrinsic, i.e. with electrical conductive fillers
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15312 : being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/1627 : stacked type assemblies, e.g. stacked multi-cavities
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A stackable tier structure comprising one or more integrated circuit die and one or more feedthrough structures is disclosed. The 1/0 pads of the integrated circuit die are electrically rerouted using conductive traces from the first side of the tier structure to a feedthrough structure comprising one ore more conductive structures. The conductive structures electrically route the integrated die pads to predetermined locations on the second side of the tier structure. The predetermined locations, such as exposed conductive pads or conductive posts, in turn, may be interconnected to a second tier structure or other circuitry to permit the fabrication of a three-dimensional microelectronic module comprising one or more stacked tiers.

Claims

1. A stackable tier structure comprising:

a tier frame comprising an opposing first tier side and second tier side,

said tier frame further comprising an integrated circuit die comprising an I/O pad and a feedthrough structure,

said feedthrough structure comprising a conductive structure for the routing of an electrical signal between said first tier side and said second tier side,

said I/O pad in electrical connection with said conductive structure by means of a conductive trace, and,

at least one exposed electrically conductive pad disposed on either of said first or second tier sides in electrical connection with said conductive structure by means of said conductive trace.

2. The stackable tier of claim 1 wherein said feedthrough structure is comprised of prefabricated conductive via structure embedded in said tier frame.

3. The stackable tier of claim 1 wherein said tier frame is comprised of a molded dielectric material.

4. The stackable tier of claim 1 wherein said tier frame is comprised of a polyimide material.

5. The stackable tier of claim 1 wherein said conductive stricture is comprised of a prefabricated outwardly projecting metallized polymer column.

6. The stackable tier of claim 1 wherein said conductive structure is comprised of a prefabricated plurality of stacked stud bumps.

7. The stackable tier of claim 1 wherein said tier frame is comprised of silicon and wherein said conductive structure is a conductive via defined in said tier frame.

8. The stackable tier of claim 7 wherein said silicon is silicon having a resistivity of grater than about 100 ohms/cm.

9. A three-dimensional stack of two or more stackable tiers comprising:

a first stackable tier structure comprised of a first tier frame comprising an opposing first tier side and second tier side,

said first tier frame further comprising a first integrated circuit die comprising a first I/O pad and a first feedthrough structure comprising a first conductive structure for the routing of an electrical signal between said first tier side and said second tier side of said first tier frame,

said first I/O pad in electrical connection with said first conductive structure by means of a first conductive trace,

a first electrically conductive pad disposed on either of said first or second tier sides of said first tier frame in electrical connection with said first conductive structure by means of said first conductive trace,

a second stackable tier structure comprised of a second tier frame comprising an opposing first tier side and second tier side,

said second tier frame further comprising a second integrated circuit die comprising a second I/O pad and a first feedthrough structure comprising a second conductive structure for the routing of an electrical signal between said first tier side and said second tier side of said second tier frame,

said second I/O pad in electrical connection with said second conductive structure by means of a second conductive trace,

a second electrically conductive pad disposed on either of said first or second tier sides of said second tier frame in electrical connection with said second conductive structure by means of said second conductive trace, and,

means for electrically connecting said first I/O pad with said second I/O pad.

10. The stack of claim 9 wherein said electrical connection means is an anisotropic conductive film.

11. The stack of claim 9 wherein said electrical connection means is an anisotropic conductive paste.

12. The stack of claim 9 wherein said electrical connection means is a metallized polymer column.

13. The stack of claim 9 where said electrical connection means is a stacked stud bump column comprising a plurality of stacked stud bumps.

14. The stack of claim 9 further comprising a thermal management layer disposed between said first stackable tier structure and said second stackable tier structure.

15. The stack of claim 9 wherein said electrical connection means comprises an outwardly projecting metallized polymer column.