Look-up table based logic macro-cells

• US 20070035329A1
• Filed: 10/13/2006
• Published: 02/15/2007
• Est. Priority Date: 12/24/2003
• Status: Active Grant

• Current Assignee: Callahan Cellular LLC (Intellectual Ventures LLC)
• Original Assignee: Viciciv Technology, Inc.
• Inventors: Madurawe, Raminda
• Granted Patent: US 7,239,175 B2
• Time in Patent Office: Days
• US Class Current: 326/40
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17732 Macroblocks
• CPC Class Codes: H03K 19/1778 Structural details for adapting physical parameters

Abstract

A programmable look up table (LUT) structure of an integrated circuit, comprising: two or more LUT circuits, each said LUT circuit comprising: one or more inputs; and a plurality of LUT values; and at least one output; and a configurable multiplexer (MUX) circuit comprising: a plurality of inputs; and one or more select signals; and one or more outputs; wherein, the output of each said LUT circuit is directly coupled to a said input of the MUX circuit. Said structure further comprising one or more data storage units, each said data storage units comprising a digital output, wherein one or more of: a said MUX circuit input is directly coupled to a said data storage unit digital output.

Claims

1. A programmable look up table (LUT) structure of an integrated circuit, comprising:

a plurality of LUT circuits, each LUT circuit comprising;

one or more logic inputs; and

two or more configurable LUT values; and

at least one output; and

one or more configurable data storage units comprising a digital output; and

a configurable multiplexer (MUX) circuit comprising;

one or more select inputs; and

one or more outputs; and

two or more inputs, wherein a first input is coupled to the output of a said LUT circuit, and a second input is coupled to the output of a said data storage unit.

2. The structure of claim 1, further comprising:

M said LUT circuits, wherein M=2^N, where N is an integer greater than one; and

M said configurable data storage devices; and

the MUX circuit comprises N said select inputs, and 2M said inputs, wherein;

each of the M said LUT circuit outputs is coupled to an input; and

each of the M said configurable data storage unit outputs is coupled to an input.

3. The structure of claim 1, wherein said MUX circuit further comprising one or more control signals configured by a configurable data storage unit.

4. The structure of claim 3, wherein said control signals can be configured to select one of said first or second input as an input to be further decoded by the MUX circuit select inputs.

5. The structure of claim 3, wherein said control signals can be configured to select a subset of the MUX circuit inputs as inputs to be further decoded and coupled to a MUX circuit output by the MUX circuit select inputs.

6. The structure of claim 3, wherein said control signals can be configured to couple one of said first or second input to a MUX circuit output.

7. The structure of claim 3, wherein all of said configurable data storage units further comprise one or more configurable memory elements.

8. The structure of claim 6, wherein said configurable memory element is one of fuse link, anti-fuse capacitor, laser-fuse, SRAM cell, DRAM cell, metal optional link, EPROM cell, EEPROM cell, flash cell, ferro-electric element, optical element, electro-chemical element, electrolytic element, Carbon nano-tube, electro-mechanical element, electromagnetic element and magnetic element.

9. A field programmable gate array (FPGA), comprising:

an interconnect structure comprising a plurality of wires; and

a plurality of programmable look up table (LUT) structures as in claim 1, each LUT structure coupled to the interconnect structure by a programmable means; and

one or more memory blocks, each memory block coupled to the interconnect structure; and

a plurality of input, output and I/O pins, each pin coupled to the interconnect structure.

10. The FPGA of claim 9, comprising one or more IP blocks coupled to the interconnect structure.

11. The FPGA of claim 9, comprising one or more registers coupled to the interconnect structure, wherein:

at least one output of a configurable multiplexer within a said LUT structure as in claim 1 is coupled to a register.

12. The FPGA of claim 9, comprising an analog circuit coupled to the interconnect structure.

13. The FPGA of claim 9, wherein a said pin is coupled to an external integrated circuit.

14. A programmable look up table (LUT) structure of an integrated circuit, comprising:

two or more LUT circuits, each said LUT circuit comprising;

one or more inputs; and

a plurality of LUT values; and

at least one output; and

a configurable multiplexer (MUX) circuit comprising;

a plurality of inputs; and

one or more select signals; and

one or more outputs;

wherein, the output of each said LUT circuit is directly coupled to a said input of the MUX circuit.

15. The structure of claim 14, wherein the MUX circuit further comprises:

one or more control signals, each said control signal configured by a data storage unit comprising a digital output.

16. The structure of claim 14, further comprising one or more data storage units, each said data storage units comprising a digital output, wherein one or more of:

a said MUX circuit input is directly coupled to a said data storage unit digital output.

17. The structure of claim 14, wherein an output of the MUX circuit is coupled to an input of a storage circuit, said storage circuit comprising:

a clock input; and

one or more control logic signals; and

at least one output, said output changing in a well defined response sequence by the input, said response sequence comprising at least one characteristic truth table from the set S-R, Clocked S-R, D, T, J-K and Clocked J-K flip-flops.

18. The structure of claim 16, wherein the configurable multiplexer circuit further comprises:

a first multiplexer circuit, comprising;

inputs of the configurable multiplexer circuit as inputs; and

a first set of two or more outputs; and

one or more control signals, each said control signal configured by a data storage unit comprising a digital output, said control signals coupling a first potion of the inputs to said first set of outputs; and

a second multiplexer circuit, comprising;

first set of outputs of the first multiplexer circuit as inputs; and

at least one output; and

select signals of the configurable multiplexer circuit as select signals.

19. The structure of claim 18, wherein the first multiplexer circuit further comprises:

a second set of one or more outputs, wherein said control signals further couple a second portion of the first multiplexer inputs to said second set of outputs.

20. The structure of claim 18, wherein all of the configurable data storage units comprises a configurable memory element selected from one of:

a fuse link, an anti-fuse capacitor, an SRAM cell, a DRAM cell, a metal optional link, an EPROM cell, an EEPROM cell, a flash cell, a ferro-electric element, an electro-chemical cell, an electromagnetic cell, a carbon nano-tube, an optical element and a magnetic element.