Method and arrangement for monitoring a power output stage

• US 20070035976A1
• Filed: 04/30/2004
• Published: 02/15/2007
• Est. Priority Date: 05/23/2003
• Status: Active Grant

• Current Assignee: Continental Automotive GmbH (Continental AG)
• Original Assignee: Siemens AG
• Inventors: Sader, Frank
• Granted Patent: US 7,514,891 B2
• Time in Patent Office: Days
• US Class Current: 363/132
• CPC Class Codes: H02H 7/0844 Fail safe control, e.g. by comparing control signal and controlled current, isolating motor on commutation error
• CPC Class Codes: H02P 29/02 Providing protection against overload without automatic interruption of supply protection against faults of stepper motors H02P8/36

Abstract

The invention relates to a method and arrangement for monitoring a power output stage, whereby the power output stage has at least one half bridge, comprising a series circuit of two semiconductor switches supplied with an operating voltage. The semiconductor switches may be alternately controlled in a conducting state and a non-conducting state, by means of pulse-width modulated pulses and the connection point of the semiconductor switch of the at least one half bridge forms an output. According to the invention, each pulse width of the signals at the output is compared with a relevant set pulse width and the power output stage is recognised as fault-free when deviations do not exceed a given magnitude.

Claims

1-9. -9. (canceled)

10. A method for monitoring a power output stage having at least one half bridge with a series circuit including two semiconductor switches, an operating voltage being applied to the series circuit, the semiconductor switches being alternately controlled into an on state and an off state by pulse width modulated pulses, wherein a junction point between the semiconductor switches of the at least one half bridge forms an output signal, said method comprising the steps of:

comparing a pulse width of the output signal to a desired pulse width; and

determining that the power output stage is fault-free if a difference between the pulse width of the output signal and the desired pulse width for each at least one half bridge is less than a prescribed level.

11. The method of claim 10, wherein said step of comparing is performed in a processor that produces the pulse width modulated pulses supplied to the semiconductor switches.

12. The method of claim 11, wherein a level of the output signal is matched to a level of the desired pulse width in said step of comparing.

13. The method of claim 10, wherein said step of comparing comprises comparing a pulse width for a plurality of periods of the output signal to a desired pulse width for the plurality of periods.

14. The method of claim 10, wherein said step of comparing is performed if the pulse widths of the output signal are constant over a period of time required for measuring the pulse width of the output signal.

15. The method of claim 10, wherein said step of comparing is performed if the pulse widths of the output signal change in a known manner over a period of time required for measuring the pulse width of the output signal.

16. The method of claim 10, wherein the desired pulse width comprises a width of the pulse width modulated pulses.

17. An arrangement for monitoring a power output stage, the power output stage having at least one half-bridge including a series circuit with two semiconductor switches, the series circuit connectable to an operating voltage, the semiconductor switches being alternately controllable into an on state and an off state by a pulse width modulated pulse signal, a junction point between the semiconductor switches of the at least one half bridge forming an output, said arrangement including a comparison device connected for receiving the output of the at least one half bridge, said comparison device comparing a pulse width of the output to a pulse width of the pulse width modulated pulse signal.

18. The arrangement of claim 17, wherein said comparison device comprises a part of a control device which produces the pulse width modulated pulse signal.

19. The arrangement of claim 17, further comprising a level-matching circuit arranged between said comparison device and the junction point between the semiconductor switches of the at least one half bridge for matching a level of the output signal to a level of the pulse width modulated pulse signal.