System and method for optically interconnecting memory devices

• US 20070035980A1
• Filed: 10/02/2006
• Published: 02/15/2007
• Est. Priority Date: 08/02/2002
• Status: Active Grant

• Current Assignee: George Taylor
• Original Assignee: George Taylor
• Inventors: Taylor, George
• Granted Patent: US 7,382,639 B2
• Time in Patent Office: Days
• US Class Current: 365/63
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1054 Optical output buffers
• CPC Class Codes: G11C 7/1069 I/O lines read out arrangements
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1081 Optical input buffers
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01055 Cesium [Cs]
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding

Abstract

A memory device includes a semiconductor substrate in which memory circuitry has been fabricated. An address converter and a control signal converter are coupled to an address decoder and control logic, respectively. The address and control converters are operable to receive and convert optical address and control signals, respectively, into corresponding electrical address signals applied to the address decoder and control signals applied to the control logic. A read/write circuit on the substrate is coupled to a data converter formed in the substrate. The data converter is operable to receive and convert optical write data signals into corresponding electrical data signals to be applied to the read/write circuit and to receive and convert electrical read data signals into corresponding optical read data signals.

Claims

1-38. -38. (canceled)

39. A memory module, comprising:

an insulative substrate;

a plurality of memory devices mounted on the substrate, each memory device comprising;

a semiconductor substrate; and

a plurality of electrical input and output signal lines fabricated on the semiconductor substrate including electrical data signal lines operable to output electrical read data signals and input electrical write data signals, and electrical address and control signal lines operable to input electrical address and control signals;

a memory hub mounted on the insulative substrate, the memory hub having an optical input/output port and a plurality of electrical input and output terminals including terminals outputting electrical write data signals, terminals inputting electrical read data signals, and terminals outputting electrical command and address signals, the memory hub being operable to receive optical input signals coupled to the input/output port and to apply corresponding electrical signals to the terminals of the memory hub, the memory hub being further operable to receive electrical signals at the terminals of the memory hub and to apply optical output signals to the input/output port; and

a plurality of signal paths coupling the terminals of the memory hub to the data, address and control signal lines on the memory devices.

40. The memory module of claim 39 wherein the optical input signals, comprise optical control, address and write data signals, and the optical output signals comprise optical read data signals.

41. The memory module of claim 39 wherein the memory devices comprise dynamic random access memory devices.

42. The memory module of claim 39 wherein each signal path comprises a plurality of conductive traces.

43. The memory module of claim 39 wherein each signal path comprises control, address and data busses.

44. The memory module of claim 39 wherein the memory hub is operable to apply electrical hub control, address and data signals to each memory device on the module simultaneously.

45. The memory module of claim 39 wherein the memory hub is operable to detect device address information in the input signal and apply electrical control, address and data signals to a corresponding memory device on the module.

46. The memory module of claim 39 wherein the insulative substrate comprises a plurality of optical paths embedded within the insulative substrate, and further wherein at least one optical path is coupled to the optical input/output port.

47-92. -92. (canceled)