LIGHT EXPOSURE MASK AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME

• US 20070037070A1
• Filed: 08/08/2006
• Published: 02/15/2007
• Est. Priority Date: 08/12/2005
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: OHNUMA, Hideto, NAGAI, Masaharu
• Granted Patent: US 7,914,971 B2
• Time in Patent Office: Days
• US Class Current: 430/5
• CPC Class Codes: G03F 1/50 Mask blanks not covered by G03F1/20 - G03F1/34; Preparation thereof
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile

Abstract

The present invention provides a light exposure mask which can form a photoresist layer in a semi-transmissive portion with uniform thickness, and a method for manufacturing a semiconductor device in which the number of photolithography steps (the number of masks) necessary for manufacturing a TFT substrate is reduced by using the light exposure mask. A light exposure mask is used, which includes a transmissive portion, a light shielding portion, and a semi-transmissive portion having a light intensity reduction function where lines and spaces are repeatedly formed, wherein the sum of a line width L of a light shielding material and a space width S between light shielding materials in the semi-transmissive portion satisfies a conditional expression (2n/3)×m≦L+S≦(6n/5)×m when a resolution of a light exposure apparatus is represented by n and a projection magnification is represented by 1/m (m≧1).

Claims

1. A light exposure mask comprising a transmissive portion, a light shielding portion, and a semi-transmissive portion,

wherein a relation between a sum of a line width L of a light shielding material and a space width S between light shielding materials in the semi-transmissive portion, n, and m satisfies a conditional expression (n/3)×

m≦

L+S≦

(3n/2)×

m when a resolution of a light exposure apparatus is represented by n and a projection magnification is represented by 1/m (m≧

1).

3. A light exposure mask according to claim 1, wherein a relation between n, m, and L satisfies L<

(2n/3)×

m.

5. A light exposure mask according to claim 1, wherein the semi-transmissive portion is arranged on a side of the light shielding portion.

7. A method for manufacturing a semiconductor device, comprising the steps of:

forming a resist pattern having a first region and a second region thinner than the first region on a side of the first region by using the light exposure mask according to claim 1;

and

selectively etching a film to be etched by using the resist pattern.

2. A light exposure mask comprising a transmissive portion, a light shielding portion, and a semi-transmissive portion,

wherein a relation between a sum of a line width L of a light shielding material and a space width S between light shielding materials in the semi-transmissive portion, n, and m satisfies a conditional expression (2n/3)×

m≦

L+S≦

(6n/5)×

m when a resolution of a light exposure apparatus is represented by n and a projection magnification is represented by 1/m (m≧

1).

4. A light exposure mask according to claim 2, wherein a relation between n, m, and L satisfies L<

(2n/3)×

m.

6. A light exposure mask according to claim 2, wherein the semi-transmissive portion is arranged on a side of the light shielding portion.

8. A method for manufacturing a semiconductor device, comprising the steps of:

forming a resist pattern having a first region and a second region thinner than the first region on a side of the first region by using the light exposure mask according to claim 2;

and

selectively etching a film to be etched by using the resist pattern.

9. A method for manufacturing a semiconductor device, comprising the steps of:

forming an insulating film over a semiconductor layer;

forming a conductive film over the insulating film;

forming over the conductive film, a resist pattern having a first region and a second region thinner than the first region on a side of the first region by using a light exposure mask including a semi-transmissive portion;

forming a gate electrode having a first region and a second region thinner than the first region on a side of the first region by etching the conductive film with the use of the resist pattern; and

injecting an impurity element into the semiconductor layer with the use of the gate electrode as a mask to form a source region and a drain region outside the gate electrode, and injecting the impurity element into the semiconductor layer through the second region of the gate electrode to form a first impurity region and a second impurity region in a region overlapped with the second region of the gate electrode,

wherein the resist pattern is formed by using the light exposure mask in which the sum of a line width L of a light shielding material and a space width S between light shielding materials in the semi-transmissive portion satisfies a conditional expression (n/3)×

m≦

L+S≦

(3n/2)×

m when a resolution of a light exposure apparatus is represented by n and a projection magnification is represented by 1/m (m≧

1).

11. A method for manufacturing a semiconductor device according to claim 9, wherein a relation between n, m, and L satisfies L<

(2n/3)×

m.

13. A method for manufacturing a semiconductor device according to claim 9, wherein each of the first and second impurity regions contains an impurity element imparting n-type or p-type conductivity at a concentration lower than that of each of the source region and the drain region.

10. A method for manufacturing a semiconductor device, comprising the steps of:

forming an insulating film over a semiconductor layer;

forming a conductive film over the insulating film;

forming over the conductive film, a resist pattern having a first region and a second region thinner than the first region on a side of the first region by using a light exposure mask including a semi-transmissive portion;

forming a gate electrode having a first region and a second region thinner than the first region on a side of the first region by etching the conductive film with the use of the resist pattern; and

injecting an impurity element into the semiconductor layer with the use of the gate electrode as a mask to form a source region and a drain region outside the gate electrode, and injecting the impurity element into the semiconductor layer through the second region of the gate electrode to form a first impurity region and a second impurity region in a region overlapped with the second region of the gate electrode,

wherein the resist pattern is formed by using the light exposure mask in which the sum of a line width L of a light shielding material and a space width S between light shielding materials in the semi-transmissive portion satisfies a conditional expression (2n/3)×

m≦

L+S≦

(6n/5)×

m when a resolution of a light exposure apparatus is represented by n and a projection magnification is represented by 1/m (m≧

1).

12. A method for manufacturing a semiconductor device according to claim 10, wherein a relation between n, m, and L satisfies L<

(2n/3)×

m.

14. A method for manufacturing a semiconductor device according to claim 10, wherein each of the first and second impurity regions contains an impurity element imparting n-type or p-type conductivity at a concentration lower than that of each of the source region and the drain region.