Multichip packages with exposed dice

• US 20070037320A1
• Filed: 10/24/2006
• Published: 02/15/2007
• Est. Priority Date: 03/17/2003
• Status: Abandoned Application

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Mostafazadeh, Shahram, Smith, Joseph
• Application Number:
  US11/586,094
• Publication Number:
  US 20070037320A1
• Time in Patent Office: Days
• US Class Current: 438/108
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2223/54493 Peripheral marks on wafers, e.g. orientation flats, notches, lot number
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3107 : the device being completely enclosed
• CPC Class Codes: H01L 23/49548 : Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 23/49575 : Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15747 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/18165 : of a wire bonded chip
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

Multichip packages and methods for making same. The present invention generally allows for either the back of a flipchip, the back of a mother die, or both to be exposed in a multichip package. When the mother die is connected to the package contacts, the back of the flip chip is higher than the electrical connections. Accordingly, the back of the flip chip can be exposed. Furthermore, if a temporary tape substrate is used with a leadframe panel that does not have a die attach pad, the package can be even thinner. Once the temporary tape substrate is removed, both the back of the flipchip and the back of the mother die will be exposed from the encapsulant.

Claims

1. A method of packaging integrated circuits comprising:

providing a semiconductor wafer that has an array of mother dice formed therein;

mounting a multiplicity of singulated daughter dice on the wafer, each daughter die being mounted on an associated mother die and electrically connected to the mother die by direct soldering using a flip chip mounting approach, wherein the daughter dice have shorter lengths and widths than the mother dice such that the mother dice have at least some contacts that are exposed relative to their respective daughter dice, and wherein the wafer having the array of mother dice has not been diced or singulated prior to the mounting of the daughter dice.

2. A method as recited in claim 1, further comprising dicing the semiconductor wafer having daughter dice mounted onto the mother dice on the wafer to create a multiplicity of individual chip stacks.

3. A method as recited in claim 1, further comprising underfilling the regions beneath the daughter dice between the daughter and mother dice at the wafer level.

4. A method of packaging integrated circuits comprising:

positioning a plurality of multi-chip stacks on a lead frame panel having a multiplicity of device areas, wherein each chip stack consists of a mother die having an active surface and a daughter die having an active surface, the active surface of the daughter die being flip chip mounted to the active surface of the mother die, and wherein each chip stack is positioned in an associated device area;

electrically connecting contacts on the mother dice of the selected chip stacks to contacts within their associated device area;

encapsulating the device areas of the lead frame panel; and

singulating the device areas after the encapsulation to create a multiplicity of individual stacked multi-chip packages.

5. A method as recited in claim 4, wherein the daughter dice have shorter lengths and widths than the mother dice such that the mother dice have at least some contacts that are exposed relative to their respective daughter dice.

6. A method as recited in claim 4, wherein the lead frame device area does not include a die attach pad and wherein positioning the chip stacks includes placing the chip stacks on a temporary tape substrate that is also adhered to a back surface of the lead frame panel, the method further comprising removing the temporary tape substrate after the encapsulation.

7. A method as recited in claim 4, wherein the encapsulation covers back surfaces of the daughter dice.

8. A method as recited in claim 4, wherein the encapsulation is arranged to expose back surfaces of the daughter dice.

9. A method as recited in claim 4, further comprising applying heat spreaders to back surfaces of the daughter dice before the encapsulation.

10. A method as recited in claim 4, wherein the resulting multi-chip packages are quad flat packs—

no lead packages.

11. A method as recited in claim 4, wherein selected multi-chip stacks are each mounted on a third die mounted within a device area of the lead frame panel, wherein contacts on said third dice are electrically connected to contacts within their associated device areas.

12. A method as recited in claim 11, further comprising electrically connecting contacts on the mother dice of the selected multi-chip stacks to contacts within their associated device areas.

13. A method as recited in claim 11, wherein a spacer is positioned between a mother die and a third die.