Structure and method for forming inter-poly dielectric in a shielded gate field effect transistor

• US 20070037327A1
• Filed: 08/09/2005
• Published: 02/15/2007
• Est. Priority Date: 08/09/2005
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Probst, Dean, Herrick, Robert, Session, Fred
• Granted Patent: US 7,385,248 B2
• Time in Patent Office: Days
• US Class Current: 438/151
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A shielded gate trench FET is formed as follows. A trench is formed in a silicon region of a first conductivity type, the trench including a shield electrode insulated from the silicon region by a shield dielectric. An inter-poly dielectric (IPD) including a layer of thermal oxide and a layer of conformal dielectric is formed along an upper surface of the shield electrode. A gate dielectric lining at least upper trench sidewalls is formed. A gate electrode is formed in the trench such that the gate electrode is insulated from the shield electrode by the IPD.

Claims

1. A method of forming a field effect transistor, comprising:

forming a trench in a silicon region of a first conductivity type, the trench having a shield electrode insulated from the silicon region by a shield dielectric;

forming an inter-poly dielectric (IPD) comprising a layer of thermal oxide and a layer of conformal dielectric along an upper surface of the shield electrode;

forming a gate dielectric lining at least upper trench sidewalls; and

forming a gate electrode in the trench, the gate electrode being insulated from the shield electrode by the IPD.

2. The method of claim 1 wherein the IPD has a concave upper surface.

3. The method of claim 1 wherein a ratio of a thickness of the IPD to a thickness of the gate dielectric is greater than three to one.

4. The method of claim 1 wherein the gate dielectric is formed after forming the IPD.

5. The method of claim 1 wherein the step of forming an IPD comprises:

forming a layer of thermal oxide along upper sidewalls of the trench and along an upper surface of the shield electrode;

filling the trench with a conformal layer of dielectric; and

partially removing the conformal layer of dielectric and the layer of thermal oxide such that the IPD comprising a remaining portion of the thermal dielectric layer and a remaining portion of the conformal layer of dielectric is formed.

6. The method of claim 5 wherein the step of forming a layer of thermal oxide comprises thermally oxidizing silicon such that a thicker layer of thermal oxide is formed along the upper surface of the shield dielectric than along the trench sidewalls.

7. The method of claim 5 wherein the partially removing step completely removes any dielectric along silicon surfaces adjacent the trench and along upper trench sidewalls.

8. The method of claim 5 wherein the filling step comprises depositing a conformal layer of oxide to fill the trench.

9. The method of claim 5 wherein the partially removing step comprises uniformly etching back the conformal layer of dielectric and the thermal oxide layer to a desired depth in the trench such that the remaining layer of conformal dielectric is surrounded by the remaining thermal oxide layer along a lower surface and sidewalls of the remaining layer of conformal dielectric.

10. The method of claim 1 wherein the step of forming a trench comprises:

forming a shield dielectric lining the trench sidewalls and bottom;

forming a shield electrode recessed in the trench; and

partially removing the exposed portions of the shield dielectric such that a thin layer of the shield dielectric remains at least along upper trench sidewalls.

11. The method of claim 1 further comprising:

forming a well region of a second conductivity type in the silicon region; and

forming source regions in the well region such that the source regions flank the trench.

12. The method of claim 11 further comprising:

forming a layer of pre-metal dielectric extending over the gate electrode, the source regions and the well region;

removing predefined portions of the pre-metal dielectric layer to expose corresponding surfaces of the well region;

recessing the well region along the exposed surfaces such that sidewalls of source regions become exposed; and

forming a metal layer to electrically contact the well region and the exposed sidewalls of the source regions.

13. A field effect transistor (FET) comprising:

a trench extending into a silicon region of a first conductivity type;

a shield electrode in a lower portion of the trench, the shield electrode being insulated from the silicon region by a shield dielectric; and

a gate electrode in the trench over but insulated from the shield electrode by an inter-poly dielectric (IPD), the IPD comprising a conformal layer of dielectric and a thermal oxide layer.

14. The FET of claim 13 wherein the gate electrode is insulated from the silicon region by a gate dielectric extending along upper trench sidewalls, and a ratio of a thickness of the IPD to a thickness of the gate dielectric is greater than three to one.

15. The FET of claim 13 wherein the IPD has a concave profile along its upper surface.

16. The FET of claim 13 wherein the gate electrode has a concave profile along its lower surface.

17. The FET of claim 13 wherein the conformal layer of dielectric is surrounded by the thermal dielectric along its lower surface and sidewalls.

18. The FET of claim 13 wherein the conformal layer of dielectric has a convex lower surface and a concave upper surface.

19. The FET of claim 13 wherein the shield electrode has a rounded top surface.

20. The FET of claim 13 wherein the silicon region comprises:

an epitaxial layer of the first conductivity type extending over a substrate of the first conductivity type;

well regions of a second conductivity type in the epitaxial layer; and

source regions of the first conductivity in the well regions, the source regions flanking the trench.

21. The FET of claim 20 wherein the trench extends into and terminates within the epitaxial layer.

22. The FET of claim 20 wherein the trench extends through the epitaxial layer and terminates within the substrate.

23. A field effect transistor (FET) comprising:

a trench extending into a silicon region of a first conductivity type;

a shield electrode in a lower portion of the trench, the shield electrode being insulated from the silicon region by a shield dielectric; and

a gate electrode in the trench over but insulated from the shield electrode by an inter-poly dielectric (IPD) having a concave profile along its upper surface.

24. The FET of claim 23 wherein the shield electrode has a rounded top surface.

25. The FET of claim 23 wherein the silicon region comprises:

an epitaxial layer of the first conductivity type extending over a substrate of the first conductivity type;

well regions of a second conductivity type in the epitaxial layer; and

source regions of the first conductivity in the well regions, the source regions flanking the trench.

26. The FET of claim 25 wherein the trench extends into and terminates within the epitaxial layer.

27. The FET of claim 25 wherein the trench extends through the epitaxial layer and terminates within the substrate.

28. A field effect transistor (FET) comprising:

a trench extending into a silicon region of a first conductivity type;

a shield electrode in a lower portion of the trench, the shield electrode being insulated from the silicon region by a shield dielectric; and

a gate electrode in the trench over but insulated from the shield electrode by an inter-poly dielectric (IPD), the IPD comprising a conformal layer of dielectric which has a convex profile along its lower surface and a concave profile along its upper surface.

29. The FET of claim 28 wherein the gate electrode has a concave profile along its lower surface.

30. The FET of claim 28 wherein the IPD further comprises a thermal dielectric surrounding the conformal layer of dielectric along its lower surface and sidewalls.

31. The FET of claim 28 wherein the silicon region comprises:

an epitaxial layer of the first conductivity type extending over a substrate of the first conductivity type;

well regions of a second conductivity type in the epitaxial layer; and

source regions of the first conductivity in the well regions, the source regions flanking the trench.

32. The FET of claim 31 wherein the trench extends into and terminates within the epitaxial layer.

33. The FET of claim 31 wherein the trench extends through the epitaxial layer and terminates within the substrate.