Process for manufacturing dual work function metal gates in a microelectronics device

• US 20070037343A1
• Filed: 08/10/2005
• Published: 02/15/2007
• Est. Priority Date: 08/10/2005
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Colombo, Luigi, Visokay, Mark, Chambers, James
• Granted Patent: US 7,229,873 B2
• Time in Patent Office: Days
• US Class Current: 438/231
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

The present invention provides a method of forming a dual work function metal gate microelectronics device 200. In one aspect, the method includes forming nMOS and pMOS stacked gate structures 315a and 315b. The nMOS and pMOS stacked gate structures 315a and 315b each comprise a gate dielectric 205, a first metal layer, 305 located over the gate dielectric 205 and a sacrificial gate layer 310 located over the first metal layer 305. The method further includes removing the sacrificial gate layer 310 in at least one of the nMOS or pMOS stacked gate structures, thereby forming a gate opening 825 and modifying the first metal layer 305 within the gate opening 825 to form a gate electrode with a desired work function.

Claims

1. A process for forming a dual work function metal gate microelectronics device, comprising:

forming a stacked gate structure in each of a pMOS region and an nMOS region of a microelectronics substrate, the gate structure comprising a gate dielectric, a first metal layer located over the gate dielectric and a sacrificial gate layer located over the first metal layer;

removing the sacrificial gate layer in at least one of the nMOS or pMOS regions, thereby forming a gate opening; and

modifying the first metal layer within the gate opening to form a gate electrode with a desired work function.

2. The process recited in claim 1 further comprising forming at least a second metal layer over the first metal layer and within the gate opening prior to modifying the first metal layer, and wherein modifying comprises incorporating a portion of the at least second metal layer into the first metal layer to form the gate electrode with the desired work function.

3. The process recited in claim 2, wherein the sacrificial gate layer is removed in the nMOS region and the second metal layer is deposited in the gate opening located in the nMOS region and incorporating forms an nMOS gate electrode with a desired nMOS work function.

4. The process recited in claim 3, wherein the second metal layer is vanadium, tantalum, niobium, titanium, zirconium, hafnium, scandium, yttrium, lanthanum, or ytterbium.

5. The process recited in claim 3, wherein the sacrificial gate layer is removed from the pMOS region and a third metal layer is deposited in the gate opening in the pMOS region and modifying comprises incorporating a portion of the third metal layer into the first metal layer to form a pMOS gate electrode with a desired pMOS work function.

6. The process recited in claim 5 wherein the third metal layer is platinum, iridium, nickel, cobalt, ruthenium, rhodium, or rhenium.

7. The process recited in claim 5, further comprising forming a metal contact in each of the nMOS and pMOS gate openings and over each of the nMOS and pMOS gate electrodes.

8. The process recited in claim 5, wherein the gate dielectric is silicon oxynitride, hafnium silicon oxynitride, hafnium oxide, hafnium oxynitride, zirconium oxide, zirconium silicon oxynitride, zirconium oxynitride, or tantalum silicon oxynitride, and the first metal layer is tungsten silicide, the second metal layer is tantalum and the third layer is platinum.

9. The process recited in claim 5 wherein incorporating the second metal layer and the third metal layer is conducted simultaneously.

10. The process recited in claim 5 wherein incorporating is conducted at a low temperature.

11. The process recited in claim 10 wherein the low temperature does not exceed about 400 degrees Celsius.

12. The process recited in claim 1 further comprising forming source/drains adjacent the stacked gate structure prior to removing the sacrificial gate layer.

13. The process recited in claim 12 further comprising forming sidewall spacers adjacent the stacked gate structure prior to removing the sacrificial gate layer.

14. The process recited in claim 13, wherein the sidewall spacers comprise silicon dioxide or silicon nitride carbide.

15. The process recited in claim 13 further comprising forming silicided contacts adjacent the stacked gate structure prior to removing the sacrificial gate layer.

16. The process recited in claim 13 wherein a material used to form the sacrificial gate layer is chosen such that the sacrificial gate layer can be selectively removed with respect to the sidewall spacers.

17. The process recited in claim 16, wherein the sacrificial gate layer is silicon nitride and the sidewall spacer comprises silicon nitride and carbon.

18. The process recited in claim 1, wherein the gate structure further comprises a barrier metal layer located between the first metal layer and the sacrificial gate layer.

19. The process recited in claim 18, wherein removing includes removing the sacrificial gate layer in both the nMOS and pMOS regions to form an nMOS gate opening and a pMOS gate opening and the method further comprises forming a second metal layer in the nMOS gate opening and the pMOS gate opening over the barrier metal layer prior to modifying the first metal layer.

20. The process recited in claim 19, wherein the first metal layer is tungsten, the barrier metal layer is tantalum nitride, and the second metal layer is tantalum, and wherein the barrier metal layer is removed from within the gate opening in the nMOS region prior to the second metal layer being deposited.

21. The process recited in claim 1, wherein the sacrificial gate layer is silicon.

22. The process recited in claim 1, wherein the sacrificial gate layer is silicon nitride, silicon carbide, silicon dioxide or silicon germanium.

23. The process recited in claim 1, wherein the first metal layer is tungsten, tungsten nitride, tungsten carbide, tungsten silicide, tantalum silicide, tantalum nitride, tantalum silicon nitride, tantalum carbide, molybdenum, molybdenum silicide, niobium silicide, molybdenum carbide, ruthenium, or ruthenium carbide.

24. The process recited in claim 1, wherein the gate dielectric is silicon oxynitride, hafnium silicon oxynitride hafnium oxide, hafnium oxynitride, zirconium oxide, zirconium silicon oxynitride, zirconium oxynitride, or tantalum silicon oxynitride, and the first metal layer comprises tungsten.

25. A process for forming an integrated circuit having dual work function metal gates, comprising:

forming transistors over a microelectronics substrate, comprising;

building a transistor gate, comprising;

forming a stacked gate structure in each of a pMOS region and an nMOS region of a microelectronics substrate, the gate structure comprising a gate dielectric, a first metal layer located over the gate dielectric and a sacrificial gate layer located over the first metal layer;

removing the sacrificial gate layer in at least one of the nMOS or pMOS regions, thereby forming a gate opening; and

modifying the first metal layer within the gate opening to form a gate electrode with a desired work function;

forming source/drains in the microelectronics substrate prior to removing the sacrificial gate layer; and

forming interconnects in dielectric layers located over the transistors to interconnect the transistors and form an operative integrated circuit.