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Testable digital delay line

  • US 20070038404A1
  • Filed: 10/11/2006
  • Published: 02/15/2007
  • Est. Priority Date: 04/29/2005
  • Status: Abandoned Application
First Claim
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1. A method for testing a digital delay line, the method comprising:

  • (a) providing a digital delay line with a plurality of delay elements and a multiplexer, wherein each delay element is comprised of an XOR gate, wherein each delay element receives a delay line input signal at a first input and receives a test signal at a second input, wherein the multiplexer receives the delay line input signal at a first input and receives an output signal from a delay element at each subsequent input;

    (b) setting the delay line input signal to the digital delay line, a test signal for each delay element, and a selection signal for the multiplexer to form a set of test input signals;

    (c) recording an output of the digital delay line associated with the set of test input signals;

    (d) repeating steps (b) and (c) for a plurality of sets of test input signals to form a pattern fault coverage; and

    (e) determining whether the digital delay line operates properly based on the pattern fault coverage.

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