Testable digital delay line

• US 20070038404A1
• Filed: 10/11/2006
• Published: 02/15/2007
• Est. Priority Date: 04/29/2005
• Status: Abandoned Application

• Current Assignee: Mohit Kapur, Seongwon Kim
• Original Assignee: Mohit Kapur, Seongwon Kim
• Inventors: Kim, Seongwon, Kapur, Mohit
• Application Number:
  US11/546,165
• Publication Number:
  US 20070038404A1
• Time in Patent Office: Days
• US Class Current: 702/117
• CPC Class Codes: G01R 31/31725 Timing aspects, e.g. clock distribution, skew, propagation delay for tester hardware G01R31/31937
• CPC Class Codes: H03K 2005/00039 having four transistors serially
• CPC Class Codes: H03K 2005/00156 using opamps, comparators, voltage multipliers or other analog building blocks

Abstract

A testable digital delay line that uses XOR gates as delay elements is provided. The use of XOR gates enables independent control of each input to the multiplexer. With test inputs that enable each delay element, the multiplexer inputs can be assigned any value during test, thus giving the delay line very robust pattern fault coverage. The XOR gate may consist of three current limiting inverters. A reference voltage generator generates constant voltages between a source voltage, bias voltages, and ground. These constant voltages decide the amount of current through the current limiting inverters. Selecting a different set of reference voltages programs a different current flowing in the current limiting inverters. This programmable current causes a programmable unit delay to be introduced by each XOR gate delay element.

Claims

1. A method for testing a digital delay line, the method comprising:

(a) providing a digital delay line with a plurality of delay elements and a multiplexer, wherein each delay element is comprised of an XOR gate, wherein each delay element receives a delay line input signal at a first input and receives a test signal at a second input, wherein the multiplexer receives the delay line input signal at a first input and receives an output signal from a delay element at each subsequent input;

(b) setting the delay line input signal to the digital delay line, a test signal for each delay element, and a selection signal for the multiplexer to form a set of test input signals;

(c) recording an output of the digital delay line associated with the set of test input signals;

(d) repeating steps (b) and (c) for a plurality of sets of test input signals to form a pattern fault coverage; and

(e) determining whether the digital delay line operates properly based on the pattern fault coverage.

2. The method of claim 1, wherein each XOR gate includes one or more current limiting elements, the method further comprising:

providing at least one bias voltage to the one or more current limiting elements.

3. The method of claim 2, wherein the one or more current limiting elements are one or more current limiting inverters.

4. The method of claim 2, wherein providing at least one bias voltage includes providing a control signal to a voltage generator, wherein the voltage generator generates the at least one bias voltage.

5. The method of claim 1, wherein each XOR gate includes one or more current limiting elements, the method further comprising:

rejecting power supply noise using the one or more current limiting elements.

6. The method of claim 1, wherein each XOR gate includes one or more current limiting elements, the method further comprising:

increasing impedance seen at current supply nodes of each XOR gate using the one or more current limiting elements.

7. The method of claim 1, wherein each XOR gate includes one or more current limiting elements, the method further comprising:

varying delay through each XOR gate by altering current in the one or more current limiting elements.

8. The method of claim 1, wherein each XOR gate includes one or more current limiting elements, the method further comprising:

optimizing slew rate using the one or more current limiting elements.

9. A testable digital delay line, comprising:

a delay line input signal;

a plurality of XOR gate delay elements, wherein a first XOR gate delay element within the plurality of XOR gate delay elements receives the delay line input, wherein the plurality of XOR gate delay elements are connected in series through a first input, and wherein each XOR gate delay element receives a test signal at a second input; and

a multiplexer, wherein the multiplexer receives the delay line input signal at a first input and receives a delayed version of the delay line input signal from an output of each XOR gate delay element at each subsequent input.

10. The testable digital delay line of claim 9, wherein the first XOR gate delay element receives the delay line input signal at a first input and receives a first test signal at a second input,

wherein a second XOR gate delay element receives the output of the first XOR gate delay element at a first input and receives a second test signal at a second input, and

wherein the multiplexer receives an output of the first XOR gate delay element at a second input and receives an output of the second XOR gate delay element at a third input.

11-18. -18. (canceled)

19. A testable digital delay line, comprising:

a delay line input signal;

a plurality of XOR gate delay elements, wherein a first XOR gate delay element within the plurality of XOR gate delay elements receives the delay line input, wherein the plurality of XOR gate delay elements are connected in series through a first input, and wherein each XOR gate delay element receives a test signal at a second input; and

a selection element, wherein the selection element switches among a plurality of input signals based on a selection signal, wherein the plurality of input signals include the delay line input signal at and a plurality of delayed versions of the delay line input signal from the plurality of XOR gate delay elements.

20. The testable digital delay line of claim 19, wherein each XOR gate delay element includes three sets of current limiting inverters.