Technique to combine instructions

• US 20070038844A1
• Filed: 08/09/2005
• Published: 02/15/2007
• Est. Priority Date: 08/09/2005
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Sperber, Zeev, Valentine, Robert, Anati, Ittai, Pribush, Gregory, Leibovitz, Amir, Oziel, Ido
• Granted Patent: US 8,082,430 B2
• Time in Patent Office: Days
• US Class Current: 712/219
• CPC Class Codes: G06F 9/3853 of compound instructions
• CPC Class Codes: G06F 9/3863 using multiple copies of the architectural state, e.g. shadow registers

Abstract

A micro-operation (uop) fusion technique. More particularly, embodiments of the invention relate to a technique to fuse two or more uops originating from two or more instructions.

Claims

1. An apparatus comprising:

a storage unit to store a plurality of instructions to be represented by a single micro-operation (uop), wherein only one of the plurality of instructions is to be decoded into one or more uops.

2. The apparatus of claim 1 wherein a destination storage location of a result of executing a first one of the plurality of instructions is a source storage location of an operand of a second one of the plurality of instructions.

3. The apparatus of claim 2 wherein the first and second one of the plurality of instructions appear adjacent to each other in program order.

4. The apparatus of claim 2 wherein the first and second one of the plurality of instructions do not appear adjacent to each other in program order.

5. The apparatus of claim 2 wherein the single uop is to be retired in an order so as to maintain correct state within a processor in which the single uop is to be executed.

6. The apparatus of claim 1 further comprising a reservation station to store operands, memory offsets, and branch targets associated with the single uop.

7. The apparatus of claim 6 further comprising an execution to execute the single uop.

8. The apparatus of claim 7 further comprising a retirement unit to commit state information resulting from executing the single uop to machine state.

9. A method comprising:

determining whether two or more instructions may be represented by a single micro-operation (uop) before decoding either of the two or more instructions;

representing the two or more instructions with a single uop.

10. The method of claim 9 wherein determining comprises examining a relationship between a source operand storage location of a first one of the two or more instructions and a result destination storage location of a second one of the two or more instructions.

11. The method of claim 10 further comprising representing the two or more instructions with a single uop.

12. The method of claim 11 further comprising decoding only one of the two or more instructions.

13. The method of claim 12 comprising reordering the single uop in relation to other uops whose execution may result in an incorrect machine state.

14. The method of claim 13 further comprising calling a service routine to generate correct machine state if the execution of the single uop will result in a condition chosen from a group comprising:

a fault, an assist, a trap.

15. The method of claim 14 wherein the service routine uses state information resulting from the execution of uop immediately before the single uop.

16. The method of claim 14 wherein the service routine uses state information resulting from execution of the single uop.

17. The method of claim 14 wherein the service routine uses state information resulting from the execution of a uop corresponding to the first in program order of the two or more instructions.

18. A system comprising:

a memory unit to store two or more instructions to be represented by a single micro-operation (uop);

a decode logic to decode only one of the two or more instructions;

a first logic to determine whether the two or more instructions are to be represented by a single uop before the one of the two or more instructions is decoded by the decode logic.

19. The system of claim 18 further comprising a processor to execute the single uop and retire the single uop such that correct processor state is maintained.

20. The system of claim 18 further comprising an audio device coupled to the memory unit.

21. The system of claim 19 wherein the processor comprises an instruction queue to store the two or more instructions adjacently to each other before being decoded by the decode logic.

22. The system of claim 19 wherein the processor comprises an instruction queue to store the two or more instructions non-adjacently to each other before being decoded by the decode logic.

23. The system of claim 18 wherein the two or more instructions comprise a first instruction to compare two operands and a second instruction to change an instruction pointer in response to the result of the compare of the two operands.

24. The system of claim 18 wherein the two or more instructions comprise a first instruction to generate a sum of a first and second operand and a second instruction to compare the sum with a third operand.

25. The system of claim 18 wherein the first logic comprises at least one instruction, which when executed by a processor causes the processor to determine whether the two or more instructions are to be represented by a single uop.

26. A machine-readable medium having stored thereon a set of instructions, which if executed by a machine cause the machine to perform a method comprising:

determining whether execution of two or more instructions represented by a single micro-operation (uop) results in a condition chosen from a group comprising;

a fault, a trap, an assist;

storing a machine state resulting from executing the single uop only if the condition did not occur.

27. The machine-readable medium of claim 26 wherein if one of the conditions occurred as a result of executing operations corresponding to a first of the two or more instructions and not a second of the two or more instructions, then storing machine state resulting from operations corresponding to the first of the two or more instructions.

28. The machine-readable medium of claim 26 wherein if one of the conditions occurred as a result of executing operations corresponding to a second of the two or more instructions, then storing machine state resulting from operations corresponding to the second of the two or more instructions.

29. The machine-readable medium of claim 26 wherein if one of the conditions occurred as a result of executing operations corresponding to a first and second instruction of the two or more instructions, then performing the first and second instructions individually instead of performing the single uop.

30. The machine-readable medium of claim 26 further comprising retiring a first and second instruction of the two or more instructions after storing the machine state.