Implementing instruction set architectures with non-contiguous register file specifiers

• US 20070038848A1
• Filed: 06/02/2006
• Published: 02/15/2007
• Est. Priority Date: 08/12/2005
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Wellman, John-David, Gschwind, Michael, Olsson, Brett, Montoye, Robert
• Granted Patent: US 7,421,566 B2
• Time in Patent Office: Days
• US Class Current: 712/225
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/3012 Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/30138 Extension of register space, e.g. register cache
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/3016 Decoding the operand specifier, e.g. specifier format
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/30174 for non-native instruction set, e.g. Javabyte, legacy code
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/30185 according to one or more bits in the instruction, e.g. prefix, sub-opcode
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/382 Pipelined decoding, e.g. using predecoding
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/384 Register renaming
• CPC Class Codes: G06F 9/3856 Reordering of instructions, e.g. using queues or age tags
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3863 using multiple copies of the architectural state, e.g. shadow registers
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

There are provided methods and computer program products for implementing instruction set architectures with non-contiguous register file specifiers. A method for processing instruction code includes processing a fixed-width instruction of a fixed-width instruction set using a non-contiguous register specifier of a non-contiguous register specification. The fixed-width instruction includes the non-contiguous register specifier.

Claims

1. A method for processing instruction code, comprising:

processing a fixed-width instruction of a fixed-width instruction set using a non-contiguous register specifier of a non-contiguous register specification,

wherein the fixed-width instruction includes the non-contiguous register specifier.

2. The method of claim 1, further comprising organizing instruction bits corresponding to the fixed-width instruction in a cache accessible by a processing unit so as to improve decoding of the instruction bits.

3. The method of claim 2, wherein said organizing step comprises imposing an ordering on the instructions bits to simplify routing of the instructions bits during processing thereof.

4. The method of claim 2, wherein said organizing step comprises duplicating at least one of the instruction bits to reflect a use as either a portion of the non-contiguous register file specifier, an opcode field, or extended opcode field.

5. The method of claim 1, further comprising:

identifying a plurality of registers using a first portion of the non-contiguous register specifier; and

selecting one of the plurality of registers using a second portion of the non-contiguous register specifier.

6. The method of claim 5, wherein the first portion of the non-contiguous register specifier includes a first contiguous sub-range of bits, and the second portion of the non-contiguous register specifier includes a second contiguous sub-range of bits.

7. The method of claim 1, further comprising performing an initial dependency analysis relating to the non-contiguous register specifier by comparing a subset of bits of the non-contiguous register specifier to a portion of another register specifier of another instruction.

8. The method of claim 7, wherein the subset of bits includes only bits from a first set of contiguous bits, and none of the bits of a second set of contiguous bits.

9. The method of claim 8, further comprising performing a second dependency analysis based on remaining bits of the non-contiguous register specifier other than those included in the subset and remaining bits of the other register specifier other than those included in the portion.

10. The method of claim 1, further comprising pre-decoding the fixed-width instruction to obtain a contiguous representation of the fixed-width instruction for storing in an instruction cache.

11. The method of claim 1, wherein the non-contiguous register specifier includes at least a first set of contiguous bits and a second set of contiguous bits separated by at least one bit not part of the non-contiguous register specifier.

12. The method of claim 11, wherein the first set of contiguous bits is specified directly by an instruction field in the fixed-width instruction, and the second set of contiguous bits is specified directly by another instruction field in the fixed-width instruction.

13. The method of claim 11, wherein the first set of contiguous bits is specified directly by an instruction field included in the fixed-width instruction, the second set of contiguous bits is specified using a deep encoding, and the method further comprises generating a set of n bits for inclusion as part of the non-contiguous register specifier from a set of m bits encoded in the fixed-width instruction, wherein n is less than m, and said generating step generates the set of n bits using a logic function decoding a plurality of extended opcodes, the plurality of extended opcodes indicating the use of a specific bit string as an extended register specifier.

14. A method for register renaming in an out-of-order processor, comprising:

translating at least one of a plurality of non-contiguous register specifiers included in a fixed-width instruction set into a contiguous logical register specifier; and

remapping a logic register name to a physical register using the contiguous logical register specifier, wherein the logic register name is specified in the fixed-width instruction set using non-contiguous fields.

15. The method of claim 14, wherein the at least one of the plurality of non-contiguous register specifiers is encoded in at least one fixed-width instruction from the fixed-width instruction set.

16. The method of claim 14, further comprising using the contiguous logical register specifier to track register usage and check pointing for recovery in the out-of-order processor.

17. The method of claim 14, wherein the at least one of the plurality of non-contiguous register specifiers includes at least a first set of contiguous bits and a second set of contiguous bits, the first and second sets being separated by at least one bit not part of the at least one of the plurality of non-contiguous register specifiers.

18. The method of claim 17, wherein the first set of contiguous bits is specified directly by an instruction field, and the second set of contiguous bits is specified directly by another instruction field.

19. A computer program product comprising a computer usable medium having computer usable program code for register renaming in an out-of-order processor, said computer program product comprising:

computer usable program code for translating at least one of a plurality of non-contiguous register specifiers included in a fixed-width instruction set into a contiguous logical register specifier; and

computer usable program code for remapping a logic register name to a physical register using the contiguous logical register specifier, wherein the logic register name is specified in the fixed-width instruction set using non-contiguous fields.

20. The computer program product of claim 19, wherein the at least one of the plurality of non-contiguous register specifiers is encoded in at least one fixed-width instruction from the fixed-width instruction set.