Ultra dense trench-gated power device with the reduced drain-source feedback capacitance and Miller charge
First Claim
1. A semiconductor device having improved and reduced Miller capacitance in a repeated cellular structure, wherein the cells of the device comprise:
- a substrate having one surface with a first layer highly doped with a first conductivity dopant and forming a drain;
a second layer over the first layer and lightly doped with a first conductivity dopant;
a third layer over the second layer and doped with a second conductivity dopant opposite in polarity to the first conductivity component, and forming a PN junction with the second layer;
a fourth layer on the opposite surface of the semiconductor substrate and highly doped with a first conductivity dopant;
a trench structure extending from the fourth layer into the substrate and dividing the fourth layer into a plurality of source regions, said trench having spaced apart sidewalls and a floor with an insulating layer on the sidewalls and floor, upper and lower conductive layers separated by a dielectric layer; and
a source metal layer over the device and in electrical contact with the fourth layer to contact the source regions and in electrical contact with the lower conductive layer of the trenches at peripheral locations around the cells of the device.
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Accused Products
Abstract
The cellular structure of the power device includes a substrate that has a highly doped drain region. Over the substrate there is a more lightly doped epitaxial layer of the same doping. Above the epitaxial layer is a well region formed of an opposite type doping. Covering the wells is an upper source layer of the first conductivity type that is heavily doped. The trench structure includes a sidewall oxide or other suitable insulating material that covers the sidewalls of the trench. The bottom of the trench is filled with a doped polysilicon shield. An interlevel dielectric such as silicon nitride covers the shield. The gate region is formed by another layer of doped polysilicon. A second interlevel dielectric, typically borophosphosilicate glass (BPSG) covers the gate. In operation, current flows vertically between the source and the drain through a channel in the well when a suitable voltage is applied to the gate.
21 Citations
17 Claims
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1. A semiconductor device having improved and reduced Miller capacitance in a repeated cellular structure, wherein the cells of the device comprise:
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a substrate having one surface with a first layer highly doped with a first conductivity dopant and forming a drain;
a second layer over the first layer and lightly doped with a first conductivity dopant;
a third layer over the second layer and doped with a second conductivity dopant opposite in polarity to the first conductivity component, and forming a PN junction with the second layer;
a fourth layer on the opposite surface of the semiconductor substrate and highly doped with a first conductivity dopant;
a trench structure extending from the fourth layer into the substrate and dividing the fourth layer into a plurality of source regions, said trench having spaced apart sidewalls and a floor with an insulating layer on the sidewalls and floor, upper and lower conductive layers separated by a dielectric layer; and
a source metal layer over the device and in electrical contact with the fourth layer to contact the source regions and in electrical contact with the lower conductive layer of the trenches at peripheral locations around the cells of the device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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Specification