Power semiconductor device with interconnected gate trenches

• US 20070040215A1
• Filed: 08/14/2006
• Published: 02/22/2007
• Est. Priority Date: 08/17/2005
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Ma, Ling, Turner, Russell, Amali, Adam
• Granted Patent: US 7,943,990 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A power semiconductor device which includes a plurality of gate trenches and a perimeter trench intersecting the gate trenches.

Claims

1. A power semiconductor device comprising:

a drift region of a first conductivity;

a base region of a second conductivity over said drift region;

a first plurality of trenches extending through said base region to said drift region;

a first perimeter trench disposed around and intersecting said first gate trenches;

a gate insulation layer formed in each gate trench adjacent said base region; and

a gate electrode residing in each first gate trench.

2. The power semiconductor device of claim 1, wherein said perimeter trench is a termination trench.

3. The power semiconductor device of claim 1, further comprising a termination trench disposed around said perimeter trench.

4. The power semiconductor device of claim 3, further comprising an EQR trench around said termination trench.

5. The power semiconductor device of claim 1, further comprising a gate bus disposed over at least a portion of said first perimeter trench and electrically connected to said gate electrode residing in said perimeter trench.

6. The power semiconductor device of claim 5, wherein said gate bus further comprises a field plate.

7. The power semiconductor device of claim 1, further comprising a gate bus disposed over at least a portion of said first perimeter trench and electrically connected to said gate electrode residing in said first perimeter trench.

8. The power semiconductor device of claim 1, wherein said gate electrode is comprised of conductive polysilicon.

9. The power semiconductor device of claim 1, wherein said gate insulation is comprised of silicon dioxide.

10. The power semiconductor device of claim 1, wherein each said gate trench includes a curved bottom portion.

11. The power semiconductor device of claim 1, further comprising an insulation body disposed at the bottom of each gate trench, said insulation body being thicker than said gate insulation.

12. The power semiconductor device of claim 1, further comprising conductive regions of said first conductivity over said body region and adjacent said each gate trench.

13. The power semiconductor device of claim 1, wherein said drift region is disposed over a substrate.

14. The power semiconductor device of claim 13, wherein said substrate is comprised of silicon.

15. The power semiconductor device of claim 1, wherein said power semiconductor device is a MOSFET.

16. The power semiconductor device of claim 1, wherein said power semiconductor device is an IGBT.

17. The power semiconductor device of claim 1, further comprising second plurality of gate trenches extending through said base region into said drift region;

a second perimeter trench disposed around and intersecting said second gate trenches;

a gate insulation layer formed in each second gate trench adjacent said base region; and

a gate electrode residing in each gate trench.