HDR/AB on multi-way shared pixels

• US 20070040922A1
• Filed: 08/22/2005
• Published: 02/22/2007
• Est. Priority Date: 08/22/2005
• Status: Abandoned Application

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Micron Technology, Inc.
• Inventors: Shah, Joey, McKee, Jeffrey
• Application Number:
  US11/207,744
• Publication Number:
  US 20070040922A1
• Time in Patent Office: Days
• US Class Current: 348/308
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14641 Electronic components shared by two or more pixel-elements, e.g. one amplifier shared by two pixel elements
• CPC Class Codes: H01L 27/14654 Blooming suppression

Abstract

The present invention, in the various exemplary embodiments, provides a pixel array architecture having multiple pixel cells with shared pixel cell components. The pixel architecture increases the potential fill factor, and in turn, the quantum efficiency of the pixel array. The common pixel components may be shared by a number of pixels in the array, and may include a shared gate for an providing anti-blooming characteristic of the pixels over conventional pixels. Embodiments include the multi-way sharing of a high dynamic range/anti-blooming gate and methods of operation.

Claims

1. A pixel array comprising:

a first photosensor for generating charge in response to applied light;

a second photosensor for generating charge in response to applied light; and

first and second high dynamic range/anti-blooming (“

HDR/AB”

) transistors respectively coupled to the first and the second photosensors for draining the generated charges away from the photosensors to a common drain region, said transistors having a common HDR/ABgate.

2. The pixel array of claim 1, wherein the first and the second photosensors are in a first row of the array.

3. The pixel array of claim 1, wherein the first and the second photosensors share a common readout circuit for reading out signals representing an amount of charge transferred from the first and the second photosensors.

4. The pixel array of claim 3, wherein the readout circuit comprises at least first and second transistors located in a first active area for transferring said charge from the photosensors and at least one third transistor located in a second active area for generating said signals in a second active area.

5. The pixel array of claim 4, wherein the first active area and the second active area are isolated physically from, but electrically connected to, one another.

6. The pixel array of claim 4, wherein the at least first and second transistors comprise storage transistors for transferring said charges to an intermediate storage node.

7. The pixel array of claim 6, further comprising first and second transfer transistors for transferring said charges from said intermediate storage node to a common floating diffusion region.

8. The pixel array of claim 4, wherein the at least one first and second transistors comprises a transfer gate.

9. The pixel array of claim 1, further comprising:

a third and a fourth photosensor for generating respective charges in response to applied light; and

third and fourth HDR/AB transistors respectively coupled to the third and fourth photosensors for draining the generated charges away from the third and fourth photosensors to said common drain region, said third and fourth HDR/AB transistors including said common HDR/AB gate.

10. The pixel array of claim 9, wherein at least two of the four photosensors share a common transfer transistor gate for transferring said generated charges to a floating diffusion region.

11. The pixel array of claim 10, wherein the common transfer transistor gate is located at a side of the at least two photosensors opposite the common HDR/AB gate.

12. The pixel array of claim 9, wherein the first and the second photosensors are row adjacent photosensors in a first row of the array.

13. The pixel array of claim 12, wherein the third and the fourth photosensors are row adjacent photosensors in a second row of the array.

14. The pixel array of claim 9, wherein the first, second, third, and fourth photosensors are associated with a respective first, second, third, and fourth readout circuit.

15. A pixel array comprising a plurality of pixel cells, arranged in a plurality of rows and columns, wherein a first row comprises:

a pixel pair comprising two pixel cells, each comprising a photosensor, the two pixel cells sharing common pixel components including;

a storage node for storing charges generated by the photosensors;

a reset transistor for resetting the charge at the storage node;

at least one transistor for reading out a value from the storage node; and

a HDR/AB gate electrically connected to the photosensors on a first side for draining charges away from the photosensors to a drain region on a second side of the HDR/AB gate.

16. The pixel array of claim 15, further comprising first and second storage gates for transferring charges from the photosensors to first and second intermediate storage nodes.

17. The pixel array of claim 16, further comprising at least one transfer transistor gate for transferring charges from the intermediate storage nodes to the storage node.

18. The pixel array of claim 15, wherein the drain region is a drain region for a reset transistor of a second row.

19. The pixel array of claim 15, wherein the storage node is adjacent the photosensors on a side opposite the HDR/AB gate.

20. The pixel array of claim 19, wherein at least a portion of the HDR/AB gate is located at an angle with respect to the first and second photosensors.

21. The pixel array of claim 15, wherein the HDR/AB gate is an electrode of a capacitor.

22. The pixel array of claim 21, wherein the capacitor is electrically connected to an adjacent pixel pair.

23. An array of pixel cells comprising:

a plurality of pixels arranged into rows and columns, the plurality including;

first, second, third, and fourth pixels having respective first, second third and fourth photosensors for generating photo-charges;

first, second, third, and fourth HDR/AB transistors for draining excess photo-charges from the first, second, third, and fourth photosensors into a drain region;

a common storage node for storing the generated photo-charges; and

at least one common transistor for reading out a signal from the common storage node representing an amount of generated photo-charges onto a column line.

24. The pixel array of claim 23, further comprising first, second, third, and fourth storage gates for respectively transferring generated charges from the first, second, third, and fourth photosensors into a respective storage region.

25. The pixel array of claim 24, further comprising a respective first, second, third, and fourth transfer transistor for respectively transferring charges from the respective first, second, third, and fourth storage regions into the common storage node.

26. The pixel array of claim 23, further comprising a readout circuit that includes at least two sets of capacitors for storing signals output on the column line.

27. The pixel array of claim 25, further comprising a switch for directing a first signal into a first set of capacitors and a second signal into a second set of capacitors.

28. An imager comprising:

an array of pixels comprising;

first and second pixels having a respective first and second photosensors for generating charge in response to applied light; and

first and second HDR/AB transistors respectively coupled to the first and the second photosensors for draining the generated charges away from the photosensors to a common drain region, said transistors having a common HDR/ABgate.

29. The imager of claim 28, wherein the array further comprises:

third and fourth pixels comprising respective third and fourth HDR/AB transistors for respective third and fourth photosensors, the third and fourth HDR/AB transistors also sharing said common HDR/AB gate.

30. The imager of claim 28, wherein the imager is a CMOS imager and the pixel cells are CMOS pixel cells.

31. The imager of claim 28, further comprising a circuit for applying an operating signal to the common HDR/AB gate to control the draining of the charges.

32. The imager of claim 31, wherein the circuit is constructed to apply a global operating signal to each of a plurality of HDR/AB gates in the array.

33. A processing system comprising:

a processor; and

an imager comprising an array of pixels, the array of pixels comprising;

first and second pixels having a respective first and second photosensors for generating charge in response to applied light; and

an HDR/AB gate electrically connected at a first side to the first and the second photosensors for draining the generated charges away from the photosensors to a drain region on a second side of the gate.

34. The processing system of claim 33, wherein the array further comprises:

a third and a fourth pixel cell comprising respective third and fourth photosensors, the third and fourth photosensors also being electrically connected to a first side of the HDR/AB gate.

35. The processing system of claim 33, wherein the imager is a CMOS imager and the pixel cells are CMOS pixel cells.

36. The processing system of claim 33, further comprising a circuit for applying an operating signal to the HDR/AB gate to control the draining of the charges.

37. A method of operating a pixel array comprising:

initiating a reset of first and second photosensors by activating a first shared HDR/AB transistor gate of respective first and second HDR/AB transistors, so that residual charges on the first and second photosensors are drained away from the photosensors into a first shared drain region; and

simultaneously initiating a reset of a third and fourth photosensors by activating a second shared HDR/AB transistor gate of respective third and fourth HDR/AB transistors, so that residual charges on the third and fourth photosensors are drained away from the photosensors into a second shared drain region.

38. The method of claim 37, wherein the reset of the first, second, third, and fourth photosensors begins an integration period for the photosensors.

39. The method of claim 38, wherein shared readout circuitry associated with the first and the second photosensors are reading out a signal representing an amount of charges generated by the photosensors concurrently with the reset initiation.

40. The method of claim 38, further comprising the acts of:

allowing the first, second, third, and fourth photosensors to generate charges during the integration period;

and transferring the charges from the photosensors to a respective storage node at the end of the integration period.

41. The method of claim 40, wherein the act of transferring the charges from the photosensors comprises activation of first, second, third, and fourth storage gates to transfer the charges to respective storage regions.

42. The method of claim 40, wherein the act of transferring the charges from the first, second, third, and fourth photosensors comprises activation of a first, second, third, and fourth transfer gate to transfer the charges to a respective floating diffusion region.

43. A method of operating a pixel array comprising:

initiating a first integration period for each of a plurality of pixels in the array by operating a plurality of HDR/AB gates of a plurality of HDR/AB transistors simultaneously, wherein each of the HDR/AB gates is shared by at least two of the plurality of HDR/AB transistors respectively for at least two adjacent pixels;

allowing photosensors formed in the plurality of pixels to integrate photo-charges during the first integration period; and

ending the first integration period for the plurality of pixels by transferring the photo-charges generated by the photosensors into a respective storage region.

44. The method of claim 43, wherein the HDR/AB gate is shared by two row adjacent pixels, each associated with an HDR/AB transistor.

45. The method of claim 43, wherein the HDR/AB gate is shared by four pixels, each associated with an HDR/AB transistor.

46. The method of claim 43, wherein the act of transferring the photo-charges comprises activation of a storage gate for each photosensor to transfer the charges to a respective intermediate storage region.

47. The method of claim 43, wherein the act of transferring the photo-charges comprises activation of a transfer gate to transfer the photo-charges to a floating diffusion region.

48. The method of claim 43, further comprising the act of initiating a second integration period.

49. The method of claim 48, further comprising the act of reading out a signal from at least one pixel representing the charges transferred at the end of the first integration period, during the second integration period.

50. The method of claim 48, wherein the act of initiating comprises activating the shared HDR/AB gate.

51. A method of operating a pixel array comprising:

integrating charge at first and second photosensors during a first charge integration period;

allowing excess generated charges to drain to a common drain region for the first and second photosensors during the first integration period; and

transferring the generated charges from the first and second photosensors to at least one storage node at the end of the first integration period.

52. The method of claim 51, further comprising the acts of:

integrating charge at third and fourth photosensor during the first charge integration period; and

allowing excess generated charges to drain to the common drain region from the third and fourth photosensors during the first integration period.

53. The method of claim 51, wherein allowing charges to drain comprises operating a respective first and second HDR/AB transistors, the transistors sharing a common anti-blooming transistor gate.

54. The method of claim 51, further comprising the act of reading out a first and second signal representing the generated charges during a second integration period.