Adaptive play-out buffers and adaptive clock operation in packet networks

• US 20070041324A1
• Filed: 06/12/2006
• Published: 02/22/2007
• Est. Priority Date: 06/10/2005
• Status: Active Grant

• Current Assignee: Microsemi Frequency And Time Corporation
• Original Assignee: Symmetricom Incorporated (Microchip Technology Incorporated)
• Inventors: Shenoi, Kishan
• Granted Patent: US 7,894,489 B2
• Time in Patent Office: Days
• US Class Current: 370/235
• CPC Class Codes: G06F 5/14 for overflow or underflow handling, e.g. full or empty flags
• CPC Class Codes: H04J 3/0632 Synchronisation of packets and cells, e.g. transmission of voice via a packet network, circuit emulation service [CES] queuing arrangements in packet switching elements H04L49/90; synchronising systems for the synchronous transmission of a pulse code modulated video signal with one or more other pulse code modulated signals H04N7/56
• CPC Class Codes: H04L 7/005 Correction by an elastic buffer

Abstract

Methods and apparatus are described for a play-out buffer. A method includes writing a data packet into a jitter buffer at a write address specified by a write address generator; incrementing the write address generator; generating the difference between the write address and a current read address specified by a read address generator; reading a data packet from the jitter buffer from the current read address specified by the read address generator; generating a new read address based on the difference between the write address and the current read address by the read address generator. An apparatus includes a jitter buffer; a write address generator for storing a write address; a read address generator for storing a current read address; a read address increment control; wherein the read address increment control sets the future read address based on the difference between the write address and the current read address. Another method of driving a numerically controlled oscillator includes providing a local clock with a clock cycle; generating a numerical value during each clock cycle; adding the numerical value to an accumulator having a most significant bit; and using the value of the most significant bit as an oscillator. Another apparatus includes a local clock with a clock cycle; a jitter buffer having a write address and a current read address; a first accumulator; a second accumulator having a most significant bit; an increment control; wherein the increment control sets an accumulation value to be added to the first accumulator based on the difference between the write address and the current read address; wherein the value of the second accumulator depends on the first accumulator; and wherein the most significant bit functions as an oscillator.

Claims

1. A method, comprising:

writing a data packet into a jitter buffer at a write address specified by a write address generator;

incrementing the write address generator;

generating the difference between the write address and a current read address specified by a read address generator;

reading a data packet from the jitter buffer from the current read address specified by the read address generator; and

generating a new read address based on the difference between the write address and the current read address by the read address generator.

2. The method of claim 1, further comprising:

selecting an action out of a predetermined list of actions based on the difference between the write address and the current read address.

3. The method of claim 2, wherein one of the series of actions comprises a controlled slip.

4. The method of claim 3, further comprising:

providing a timer;

assigning a threshold value T;

selecting an action based on the difference Δ

n between the write address and the current read address from the following list of actions;

if |Δ

n|≧

T, increment the read address generator;

if T≧

|Δ

n|≧

0 and the timer has expired, perform a controlled slip, else increment the read address generator;

if Δ

n=0, reset the jitter buffer by re-centering.

5. The method of claim 3, further comprising:

providing a timer;

assigning threshold values T₂ and T₁, where T₂>

T₁;

selecting an action based on the difference Δ

n between the write address and the current read address from the following list of actions;

if |Δ

n|≧

T₂, incrementing the read address generator;

if T₂≧

|Δ

n|≧

T₁, check the timer

if the timer has expired, perform a controlled slip, else increment the read address generator;

if T₁≧

Δ

n|≧

0, check the timer

if the timer has expired, perform a controlled slip and signal need for a packet loss concealment, else increment the read address generator;

if Δ

n=0, reset the jitter buffer by re-centering.

6. The method of claim 3, further comprising:

providing a timer;

providing a flag for the data packet;

assigning threshold values T₃, T₂, T₁, where T₃>

T₂>

T₁;

selecting an action based on the difference Δ

n between the write address and the current read address from the following list of actions;

if |Δ

n|≧

T₃, incrementing the read address generator;

if T₃≧

|Δ

n|≧

T₂, check the flag and the timer

if the flag is true and if the timer has expired, perform a controlled slip, else increment the read address generator;

if T₂≧

|Δ

n|≧

T₁, check the timer

if the timer has expired, perform a controlled slip, else increment the read address generator;

if T₁≧

|Δ

n|≧

0, check the timer

if the timer has expired, perform a controlled slip and signal need for packet loss concealment, else increment the read address generator;

if Δ

n=0, reset the jitter buffer by re-centering.

7. The method of claim 4, wherein the value for T is set to (½

)N, wherein 2N is the size of the jitter buffer.

8. The method of claim 5, wherein the values for T₂ and T₁ are (½

)N and (¼

)N respectively, where 2N is the size of the jitter buffer.

9. The method of claim 6, wherein the values for T₃, T₂ and T₁ are (¾

)N, (½

)N and (¼

)N respectively, where 2N is the size of the jitter buffer.

10. The method of claim 6, wherein the values for T₃, T₂ and T₁ are (⅞

)N, (¾

)N and (⅛

)N respectively, where 2N is the size of the jitter buffer.

11. The method of claim 1, wherein the jitter buffer is a dual-port RAM device.

12. The method of claim 1, wherein the jitter buffer is organized as a modulo-2N circular buffer.

13. The method of claim 3, wherein the controlled slip is carried out by incrementing the read address generator zero times if the difference between the write address and the current read address is positive and incrementing the read address generator two times if the difference between the write address and the current read address is negative.

21. A computer program, comprising computer or machine readable program elements translatable for implementing the method of claim 1.

22. An electromagnetic waveform produced by the method of claim 1.

23. A machine readable medium, comprising a program for performing the method of claim 1.

14. A method, comprising:

writing a data packet into a jitter buffer at a write address specified by a write address generator;

incrementing the write address generator;

generating the difference between the write address and a current read address specified by a read address generator;

reading a data packet from the jitter buffer from the current read address specified by the read address generator;

providing a timer;

providing a flag for the data packet;

assigning threshold values T₃, T₂, T₁, where T₃>

T₂>

T₁; and

generating a new read address based on the difference Δ

n between the write address and the current read address from the following list of actions;

if |Δ

n|≧

T₃, incrementing the read address generator;

if T₃≧

|Δ

n|≧

T₂, check the flag and the timer

if the flag is true and if the timer has expired, perform a controlled slip, else increment the read address generator;

if T₂≧

|Δ

n|≧

T₁, check the timer

if the timer has expired, perform a controlled slip, else increment the read address generator;

if T₁≧

|Δ

n|≧

0, check the timer

if the timer has expired, perform a controlled slip and signal need for packet loss concealment, else increment the read address generator;

if Δ

n=0, reset the jitter buffer by re-centering.

15. An apparatus comprising:

a jitter buffer;

a write address generator for storing a write address;

a read address generator for storing a current read address; and

a read address increment control,

wherein the read address increment control sets the future read address based on the difference between the write address and the current read address.

16. The apparatus of claim 15, wherein the read address increment control further comprises a state selector which selects an action out of a predetermined list of actions based on the difference between the write address and the current read address.

17. The apparatus of claim 16, wherein the read address increment control further comprises a subsystem for performing a controlled slip.

18. The apparatus of claim 17, further comprising a resetting timer and a subsystem which allows controlled slips only if the timer is expired.

19. The apparatus of claim 15, wherein the jitter buffer is a dual-port RAM device.

20. The apparatus of claim 15, wherein the jitter buffer is organized as a modulo-2N circular buffer.

24. An integrated circuit, comprising the apparatus of claim 15.

25. A circuit board, comprising the integrated circuit of claim 24.

26. A computer, comprising the circuit board of claim 35.

27. A network, comprising the computer of claim 26.