Networking methods and systems

• US 20070041435A1
• Filed: 10/31/2006
• Published: 02/22/2007
• Est. Priority Date: 07/18/2002
• Status: Active Grant

• Current Assignee: ParkerVision, Inc.
• Original Assignee: ParkerVision, Inc.
• Inventors: Sorrells, David, Parker, Jeffrey
• Granted Patent: US 8,160,196 B2
• Time in Patent Office: Days
• US Class Current: 375/219
• CPC Class Codes: H04B 1/30 for homodyne or synchrodyne receivers demodulator circuits H03D1/22
• CPC Class Codes: H04L 27/00 Modulated-carrier systems

Abstract

A network system includes integrated radio transceivers and digitizers, integrated baseband processors and device controllers, digital interfaces there between, and architectures and partitions for same. Licensing methodologies are provided for implementing the features described herein, and for other products and services.

Claims

1. A network system, comprising:

a direct conversion radio transceiver coupled to a digitizer, integrated within a first integrated device;

a medium access controller coupled between a baseband processor and digital control circuitry, integrated within a second integrated device; and

a digital interface that couples said first integrated device to said second integrated device.

2. The network system according to claim 1, wherein said first integrated device comprises a multi-chip module.

3. The network system according to claim 1, wherein said first integrated device comprises an integrated circuit.

4. The network system according to claim 1, wherein said second integrated device comprises an integrated circuit.

5. The network system according to claim 1, wherein said digital interface comprises a serial bus.

6. The network system according to claim 1, wherein said digital interface comprises a parallel bus.

7. The network system according to claim 1, wherein said digital interface comprises a hybrid serial/parallel bus.

8. The network system according to claim 1, wherein said digital interface comprises a multiplexed bus.

9. The network system according to claim 1, wherein said digital interface comprises a direct connection between said first and second integrated devices.

10. The network system according to claim 1, wherein said digital interface is an all-digital interface.

11. The network system according to claim 1, wherein said direct conversion radio transceiver comprises a receive path coupled between said digitizer and an antenna system, said receive path including:

a low noise amplifier coupled to said antenna system;

an automatic gain control module coupled to said low noise amplifier;

in-phase and quadrature-phase direct down-converters coupled to said automatic gain control module; and

receive analog circuitry coupled between said in-phase and quadrature-phase direct down-converters and said digitizer.

12. The network system according to claim 1, wherein said direct conversion radio transceiver comprises a transmit path coupled between said digitizer and an antenna system, said transmit path including:

transmit analog circuitry coupled to said digitizer;

in-phase and quadrature-phase direct up-converters coupled to said transmit analog circuitry; and

power amplifier circuitry coupled between outputs of said in-phase and quadrature-phase direct up-converters and said antenna system.

13. The network system according to claim 11, wherein said direct conversion radio transceiver further comprises a transmit path coupled between said digitizer and said antenna system, said transmit path including:

transmit analog circuitry coupled to said digitizer;

in-phase and quadrature-phase direct up-converters coupled to said transmit analog circuitry; and

power amplifier circuitry coupled between outputs of said in-phase and quadrature-phase direct up-converters and said antenna system.

14. The network system according to claim 13, wherein said direct conversion radio transceiver further comprises:

a clock generator coupled to said in-phase and quadrature-phase direct down-converters and to said in-phase and quadrature-phase direct up-converters; and

a frequency synthesizer coupled to said clock generator.

15. The network system according to claim 1, wherein said digitizer comprises:

a in-phase receive path analog-to-digital converter;

a quadrature-phase receive path analog-to-digital converter;

a in-phase transmit path digital-to-analog converter; and

a quadrature-phase transmit path digital-to-analog converter.

16. The network system according to claim 15, wherein said digitizer further comprises an automatic gain control digital-to-analog converter.

17. The network system according to claim 15, wherein said digital interface comprises transceiver-side digital interface circuitry, including:

a plurality of latches coupled to said digital-to-analog converters and to said analog-to-digital converters;

a bi-directional bus driver coupled between said plurality of latches and a bi-directional bus; and

address control and timing circuitry coupled to said latches.

18. The network system according to claim 17, wherein said digital interface further comprises controller-side digital interface circuitry, including:

a second bi-directional bus driver coupled to said bi-directional bus;

a second plurality of latches coupled between said second bi-directional bus driver and said baseband processor; and

second address control and timing circuitry coupled to said second plurality of latches.

19. The network system according to claim 1, wherein said second integrated device comprises an internal system bus coupled between said medium access controller and said controller.

20. A network system, comprising:

a direct conversion radio transceiver;

a baseband processor;

a digitizer coupled between said direct conversion radio transceiver and said baseband processor; and

a digital interface coupled to said baseband processor, said digital interface configured to couple to a medium access controller;

wherein said direct conversion radio transceiver, said baseband processor, and said digitizer are integrated in an integrated device.

21. The network system according to claim 20, wherein said integrated device comprises a multi-chip module.

22. The network system according to claim 20, wherein said integrated device comprises an integrated circuit.

23. The network system according to claim 20, wherein said digital interface comprises a serial bus.

24. The network system according to claim 20, wherein said digital interface comprises a parallel bus.

25. The network system according to claim 20, wherein said digital interface comprises a hybrid serial/parallel bus.

26. The network system according to claim 20, wherein said digital interface comprises a multiplexed bus.

27. The network system according to claim 20, wherein said digital interface comprises a direct connection between said baseband processor and said medium access controller.

28. The network system according to claim 20, wherein said digital interface is an all-digital interface.

29. The network system according to claim 20, wherein said direct conversion radio transceiver comprises a receive path coupled between said digitizer and an antenna system, said receive path including:

a low noise amplifier coupled to said antenna system;

an automatic gain control module coupled to said low noise amplifier;

in-phase and quadrature-phase direct down-converters coupled to said automatic gain control module; and

receive analog circuitry coupled between said in-phase and quadrature-phase direct down-converters and said digitizer.

30. The network system according to claim 20, wherein said direct conversion radio transceiver comprises a transmit path coupled between said digitizer and an antenna system, said transmit path including:

transmit analog circuitry coupled to said digitizer;

in-phase and quadrature-phase direct up-converters coupled to said transmit analog circuitry; and

power amplifier circuitry coupled between outputs of said in-phase and quadrature-phase direct up-converters and said antenna system.

31. The network system according to claim 29, wherein said direct conversion radio transceiver further comprises a transmit path coupled between said digitizer and said antenna system, said transmit path including:

transmit analog circuitry coupled to said digitizer;

in-phase and quadrature-phase direct up-converters coupled to said transmit analog circuitry; and

power amplifier circuitry coupled between outputs of said in-phase and quadrature-phase direct up-converters and said antenna system.

32. The network system according to claim 31, wherein said direct conversion radio transceiver further comprises:

a clock generator coupled to said in-phase and quadrature-phase direct down-converters and to said in-phase and quadrature-phase direct up-converters; and

a frequency synthesizer coupled to said clock generator.

33. The network system according to claim 20, wherein said digitizer comprises:

a in-phase receive path analog-to-digital converter;

a quadrature-phase receive path analog-to-digital converter;

a in-phase transmit path digital-to-analog converter; and

a quadrature-phase transmit path digital-to-analog converter.

34. The network system according to claim 33, wherein said digitizer further comprises an automatic gain control digital-to-analog converter.

35. The network system according to claim 33, wherein said digital interface comprises transceiver-side digital interface circuitry, including:

a plurality of latches coupled to said baseband processor;

a bi-directional bus driver coupled between said plurality of latches and a bi-directional bus; and

address control and timing circuitry coupled to said latches.

36. The network system according to claim 35, wherein said digital interface further comprises controller-side digital interface circuitry, including:

a second bi-directional bus driver coupled to said bi-directional bus;

a second plurality of latches coupled between said second bi-directional bus driver and said medium access controller; and

second address control and timing circuitry coupled to said second plurality of latches.

37. The network system according to claim 20, wherein said second integrated device comprises an internal system bus coupled between said medium access controller and said controller.