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High-speed serial data receiver architecture

  • US 20070041455A1
  • Filed: 02/23/2006
  • Published: 02/22/2007
  • Est. Priority Date: 08/03/2005
  • Status: Active Grant
First Claim
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1. High-speed serial data signal receiver circuitry for a PLD comprising:

  • a plurality of equalizer circuits connected in series, each of the equalizer circuits being individually controllable with respect to at least one equalization characteristic performed by that equalizer circuit; and

    a loop-back connection from serial data signal transmitter circuitry of the PLD to a point intermediate two of the equalizer circuits.

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