High-speed serial data receiver architecture

• US 20070041455A1
• Filed: 02/23/2006
• Published: 02/22/2007
• Est. Priority Date: 08/03/2005
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Tran, Thungoc, Wong, Wilson, Patel, Rakesh, Shumarayev, Sergey, Maangat, Simardeep
• Granted Patent: US 7,702,011 B2
• Time in Patent Office: Days
• US Class Current: 375/257
• CPC Class Codes: H04L 1/243 at the transmitter, using a loop-back
• CPC Class Codes: H04L 25/03878 Line equalisers; line build-out devices

Abstract

Serial data signal receiver circuitry for inclusion on a PLD includes a plurality of equalizer circuits that are connected in series and that are individually controllable so that collectively they can compensate for a wide range of possible input signal attenuation characteristics. Other circuit features may be connected in relation to the equalizer circuits to give the receiver circuitry other capabilities. For example, these other features may include various types of loop-back test circuits, controllable termination resistance, controllable common mode voltage, and a controllable threshold for detection of an input signal. Various aspects of control of the receiver circuitry may be programmable.

Claims

1. High-speed serial data signal receiver circuitry for a PLD comprising:

a plurality of equalizer circuits connected in series, each of the equalizer circuits being individually controllable with respect to at least one equalization characteristic performed by that equalizer circuit; and

a loop-back connection from serial data signal transmitter circuitry of the PLD to a point intermediate two of the equalizer circuits.

2. The circuitry defined in claim 1 wherein the point is between a next-to-last of the equalizer circuits in the series and a last of the equalizer circuits in the series.

3. The circuitry defined in claim 2 wherein the series includes at least one more of the equalizer circuits preceding the next-to-last equalizer circuit.

4. The circuitry defined in claim 3 further comprising:

a second loop-back connection from an output of a last one of the equalizer circuits in the series to serial data signal transmitter circuitry of the PLD.

5. High-speed serial data signal receiver circuitry for a PLD comprising:

a plurality of equalizer circuits connected in series, each of the equalizer circuits being individually controllable with respect to at least one equalization characteristic performed by that equalizer circuit; and

signal detect circuitry connected to a point intermediate two of the equalizer circuits.

6. The circuitry defined in claim 5 wherein the point is between an initial one of the equalizer circuits in the series and a next-to-initial one of the equalizer circuits in the series

7. The circuitry defined in claim 6 wherein the series includes at least one more of the equalizer circuits following the next-to-initial equalizer circuit.

8. The circuitry defined in claim 7 wherein the at least one controllable equalization characteristic of at least the initial and next-to-initial equalizer circuits includes DC gain of those equalizer circuits.

9. The circuitry defined in claim 8 wherein DC gain of the at least one more equalizer circuit is fixed.

10. The circuitry defined in claim 6 wherein the data signal comprises a differential signal pair, and wherein the circuitry further comprises:

termination resistor circuitry connected between the pair and having controllable resistance.

11. The circuitry defined in claim 10 wherein the termination resistor circuitry includes a common mode voltage node having a low impedance connection to ground potential.

12. The circuitry defined in claim 11 wherein the connection includes controllable voltage source circuitry connected in series between the common mode voltage mode and the ground potential.

13. The circuitry defined in claim 5 wherein the at least one controllable equalization characteristic is programmable to at least some degree.

14. The circuitry defined in claim 10 wherein the controllable resistance is programmable to at least some degree.

15. The circuitry defined in claim 12 wherein the voltage of the controllable voltage source is programmable to at least some degree.

16. The circuitry defined in claim 5 wherein the signal detect circuitry employs a controllable threshold to determine whether or not a signal is detected.

17. The circuitry defined in claim 16 wherein the controllable threshold is programmable to at least some degree.

18. High-speed serial data signal receiver circuitry for a PLD comprising:

a plurality of equalizer circuits connected in series, each of the equalizer circuits being individually controllable with respect to at least one equalization characteristic performed by that equalizer circuit; and

adaptive dispersion compensation engine circuitry connected to a point intermediate two of the equalizer circuits.

19. The circuitry defined in claim 18 wherein the point is between a next-to-last of the equalizer circuits in the series and a last of the equalizer circuits in the series.

20. The circuitry defined in claim 19 wherein the series includes at least one more of the equalizer circuits preceding the next-to-last equalizer circuit.

21. The circuitry defined in claim 19 wherein the adaptive dispersion compensation engine circuitry includes dummy equalizer in circuitry.