Non-intrusive plasma monitoring system for arc detection and prevention for blanket CVD films

• US 20070042131A1
• Filed: 08/22/2005
• Published: 02/22/2007
• Est. Priority Date: 08/22/2005
• Status: Abandoned Application

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Kim, Bok Hoen, M'Saad, Hichem, Reiter, Steven, Soo, Jyr Hong, Foster, Jason, Nguyen, Vu Ngoc
• Application Number:
  US11/208,835
• Publication Number:
  US 20070042131A1
• Time in Patent Office: Days
• US Class Current: 427/569
• CPC Class Codes: H01J 37/32935 Monitoring and controlling tubes by information coming from the object and/or discharge

Abstract

Methods and systems of diagnosing an arcing problem in a semiconductor wafer processing chamber are described. The methods may include coupling a voltage probe to a process-gas distribution faceplate in the processing chamber, and activating an RF power source to generate a plasma between the faceplate and a substrate wafer. The methods may also include measuring the DC bias voltage of the faceplate as a function of time during the activation of the RF power source, where a spike in the measured voltage at the faceplate indicates an arcing event has occurred in the processing chamber. Methods and systems to reduce arcing in a semiconductor wafer processing chamber are also described.

Claims

1. A method of diagnosing an arcing problem in a semiconductor wafer processing chamber, the method comprising:

coupling a voltage probe to a process-gas distribution faceplate in the processing chamber;

activating an RF power source to generate a plasma between the faceplate and a substrate wafer; and

measuring the DC bias voltage of the faceplate as a function of time during the activation of the RF power source, wherein a spike in the measured voltage at the faceplate indicates an arcing event has occurred in the processing chamber.

2. The method of claim 1, wherein the semiconductor wafer processing chamber is a plasma-enhanced chemical vapor deposition chamber.

3. The method of claim 1, wherein the DC bias voltage of the faceplate is measured at a sampling rate of about 100 kHz or more.

4. The method of claim 1, further comprising adjusting a power ramp rate for the RF power source in response to the arcing event.

5. The method of claim 4, wherein the power ramp rate for the RF power source comprises a low-frequency ramp rate to provide low-frequency RF power in the processing chamber, and a high-frequency ramp rate to provide high-frequency RF power in the processing chamber.

6. The method of claim 5, wherein the low-frequency ramp rate is about 250 watts/second or less.

7. The method of claim 5, wherein the high-frequency ramp rate is about 600 watts/second or less.

8. The method of claim 1, further comprising adjusting a RF power level of the RF power source in response to the arcing event.

9. The method of claim 8, wherein the adjustment of the RF power level comprises reducing a low-frequency RF power level by about 25% or more.

10. The method of claim 1, further comprising adjusting a flow rate for a plasma precursor in response to the arcing event.

11. The method of claim 10, wherein the plasma precursor comprises tetraethylorthosilicate (TEOS).

12. The method of claim 10, wherein the plasma precursor comprises SiF₄.

13. The method of claim 1, wherein the voltage probe does not contact the plasma.

14. A system to diagnose an arcing problem in a semiconductor wafer processing chamber, the system comprising:

a voltage probe coupled to a process-gas distribution faceplate in the processing chamber; and

a voltage measurement device to measure the DC bias voltage of the faceplate as a function of time; and

a display coupled to the voltage measurement device to display a plot of faceplate voltage measurements as a plasma is generated in the processing chamber, wherein a spike in the plot indicates an arcing event has occurred in the processing chamber.

15. The system of claim 14, wherein the voltage measurement device measures the DC bias voltage of the faceplate at a sampling rate of about 100 kHz or more.

16. The system of claim 14, wherein the voltage probe does not contact the plasma.

17. The system of claim 14, wherein the semiconductor wafer processing chamber is a plasma-enhanced chemical vapor deposition chamber.

18. A method to reduce arcing in a semiconductor wafer processing chamber, the method comprising:

measuring a spike in a DC bias voltage of a process-gas distribution faceplate as a plasma is formed in the processing chamber, wherein the spike indicates there is arcing in the chamber;

adjusting a flow rate of a plasma precursor material supplied to the chamber; and

adjusting a ramp rate for RF power supplied to the chamber to form the plasma from the plasma precursor material.

19. The method of claim 18, wherein the method further comprises reducing an RF power level supplied to the chamber to form the plasma.

20. The method of claim 18, wherein the adjustment of the ramp rate for the RF power comprises decreasing a low-frequency RF power ramp rate to about 250 watts/second or less, and decreasing a high-frequency RF power ramp rate to about 600 watts/second or less.