Method of manufacturing a trench transistor having a heavy body region

• US 20070042551A1
• Filed: 08/10/2006
• Published: 02/22/2007
• Est. Priority Date: 11/14/1997
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Brian Mo, Dean Probst, Duc Chau, Izak Bencuya, Steven Sapp
• Inventors: Probst, Dean, Sapp, Steven, Chau, Duc, Bencuya, Izak, Mo, Brian
• Granted Patent: US 7,736,978 B2
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.

Claims

1. A trenched field effect transistor comprising:

a semiconductor substrate;

a trench extending a predetermined depth into said semiconductor substrate;

a pair of doped source junctions, positioned on opposite sides of the trench;

a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of said heavy body extending less deeply into said semiconductor substrate than said predetermined depth of said trench; and

a doped well surrounding the heavy body beneath the heavy body.

3. The trenched field effect transistor of claim 1 wherein the depth of the heavy body region relative to the depths of the well and the trench is selected so that the peak electric field when voltage is applied to the transistor will be spaced from the trench.

4. The trenched field effect transistor of claim 1 wherein said doped well has a depth less than the predetermined depth of said trench.

5. The trenched field effect transistor of claim 1 wherein said trench has rounded top and bottom corners.

6. The trenched field effect transistor of claim 1 wherein there is an abrupt junction at the interface between the heavy body and the well, to cause the peak electric field when voltage is applied to the transistor to occur in the area of the interface.

7. The trenched field effect transistor of claim 6 wherein said abrupt junction has a sheet resistance profile substantially as shown in FIG. 5.

2. The trenched field effect transistor of claim t wherein said doped well has a substantially flat bottom.

8. An array of transistor cells comprising:

a semiconductor substrate;

a plurality of gate-forming trenches arranged substantially parallel to each other and extending in a first direction, the space between adjacent trenches defining a contact area, each trench extending a predetermined depth into said substrate, the predetermined depth being substantially the same for all of said gate-forming trenches;

surrounding each trench, a pair of doped source junctions, positioned on opposite sides of the trench and extending along the length of the trench;

positioned between each pair of gate-forming trenches, a doped heady body positioned adjacent each source junction, the deepest portion of each said heavy body extending less deeply into said semiconductor substrate than said predetermined depth of said trenches;

a doped well surrounding each heavy body beneath the heavy body; and

p+ and n+ contacts disposed at the surface of the semiconductor substrate and arranged in alternation along the length of the contact area.

9. The array of transistor cells of claim 8, wherein each said doped well has a substantially flat bottom.

10. The array of transistor cells of claim 8 wherein the depth of each heavy body region relative to the depths of the wells and the gate-forming trenches is selected so that the peak electric field when voltage is applied to the transistor will occur approximately halfway between adjacent gate-forming trenches.

11. The array of transistor cells of claim 8 wherein each said doped well has a depth less than the predetermined depth of said gate-forming trenches.

12. The array of transistor cells of claim 8 wherein each said gate-forming trench has rounded top and bottom corners.

13. The array of transistor cells of claim 8 wherein there is an abrupt junction at each interface between the heavy body and the well, to cause the peak electric field when voltage is applied to the transistor to occur in the area of the interface.

14. The array of transistor cells of claim 8 further comprising a field termination structure surrounding the periphery of the array.

15. The array of transistor cells of claim 14 wherein said field termination structure comprises a well having a depth greater than that of the gate-forming trenches.

16. The array of transistor cells of claim 14 wherein said field termination structure comprises a termination trench extending continuously around the periphery of the array.

17. The array of transistor cells of claim 16 wherein said field termination structure comprises a plurality of concentrically arranged termination trenches.

18. A semiconductor die comprising:

a plurality of DMOS transistor cells arranged in an array on a semiconductor substrate, each DMOS transistor cell including a gate-forming trench, each of said gate-forming trenches having a predetermined depth, the depth of all of the gate-forming trenches being substantially the same; and

surrounding the periphery of the array, a field termination structure that extends into the semiconductor substrate to a depth that is deeper than said predetermined depth of said gate-forming trenches.

19. The semiconductor die of claim 18 wherein said field termination structure comprises a doped well.

20. The semiconductor die of claim 18 wherein said field termination structure comprises a termination trench.

21. The semiconductor die of claim 20 wherein said field termination structure comprises a plurality of concentrically arranged termination trenches.

22. The semiconductor die of claim 18 wherein each of said DMOS transistor cells further comprises a doped heavy body and said doped heavy body extends into said semiconductor substrate to a depth that is less than the predetermined depth of said gate-forming trenches.

23. A method of making a heavy body structure for a trenched DMOS transistor comprising:

providing a semiconductor substrate;

implanting into a region of the substrate a first dopant at a first energy and dosage; and

subsequently implanting into said region a second dopant at a second energy and dosage, said second energy and dosage being relatively less than said first energy and dosage.

24. The method of claim 23 wherein said fast and second dopants both comprise boron.

25. The method of claim 23 wherein said first energy is from about 150 to 200 keV.

26. The method of claim 25 wherein said first dosage is from about 1E15 to 5E15.

27. The method of claim 23 wherein said second energy is from about 20 to 40 keV.

28. The method of claim 27 wherein said second dosage is from about 1E14 to 1E15.

29. A method of making a source for a trenched DMOS transistor comprising:

providing a semiconductor substrate;

implanting into a region of the substrate a first dopant at a first energy and dosage; and

subsequently implanting into said region a second dopant at a second energy and dosage, said second energy and dosage being relatively less than said first energy and dosage.

30. The method of claim 29 wherein said first dopant comprises arsenic and said second dopant comprises phosphorus.

31. The method of claim 29 wherein said first energy is from about 80 to 120 keV.

32. The method of claim 29 wherein said first dosage is from about 5E15 to 1E16.

33. The method of claim 29 wherein said second energy is from about 40 to 70 keV.

34. The method of claim 33 wherein said second dosage is from about 1E15 to 5E15.

35. The method of claim 29 wherein the resulting depth of said source is from about 0.4 to 0.8 μ

m in the finished DMOS transistor.

36. A method of manufacturing a trenched field effect transistor comprising:

forming a field termination junction around the perimeter of a semiconductor substrate;

forming an epitaxial layer on the semiconductor substrate;

patterning and etching a plurality of trenches into the epitaxial layer;

depositing polysilicon to fill the trenches;

doping the polysilicon with a dopant of a first type;

patterning the substrate and implanting a dopant of a second, opposite type to form a plurality of wells interposed between adjacent trenches;

patterning the substrate and implanting a dopant of the second type to form a plurality of second dopant type contact areas and a plurality of heavy bodies positioned above the wells, each heavy body having an abrupt junction with the corresponding well;

patterning the substrate and implanting a dopant of the first type to provide source regions and first dopant type contact areas; and

applying a dielectric to the surface of the semiconductor substrate and patterning the dielectric to expose electrical contact areas.

37. The method of manufacturing a trenched field effect transistor of claim 36, wherein the trenches are patterned to extend in one direction and be substantially parallel to each other.

38. The method of manufacturing a trenched field effect transistor of claim 36, wherein the patterning and implanting steps further comprise arranging the fast dopant type contact areas and second dopant type contact areas in alternation and extend linearly between adjacent trenches.

39. The method of manufacturing a trenched field effect transistor of claim 36, wherein the implanting step for forming the heavy bodies comprises implanting a first dopant at a first energy and dosage and a second dopant at a second energy and dosage, the second energy and dosage being relatively less than the first energy and dosage.

40. The method of manufacturing a trenched field effect transistor of claim 36, wherein the implanting step for forming the source regions comprises implanting a first dopant at a first energy and dosage and a second dopant at a second energy and dosage, the second energy and dosage being relatively less than the first energy and dosage.

41. The method of manufacturing a trenched field effect transistor of claim 36, wherein the heavy bodies are formed prior to forming the source regions.

42. The method of manufacturing a trenched field effect transistor of claim 36 wherein the source regions are formed prior to the heavy bodies.

43. The method of manufacturing a trenched field effect transistor of claim 36 wherein said field termination is formed by forming a trench ring.

44. The method of manufacturing a trenched field effect transistor of claim 36 wherein said field termination is formed by forming a deep well doped with a dopant of the second dopant type.

45. The method of manufacturing a trenched field effect transistor of claim 36 wherein said dielectric is applied before the steps of forming the heavy bodies and second dopant type contacts, and the dielectric provides a mask for the patterning of the heavy bodies and second dopant type contacts.

46. A method of manufacturing a trench transistor comprising:

forming a plurality of trenches defined by a corresponding plurality of semiconductor mesas, a height of the plurality of mesas defining a depth of the plurality of trenches, the mesas having dopants of the first conductivity type;

lining each of the plurality of trenches with a thin layer of gate dielectric material;

substantially filling each dielectric-lined trench with conductive material to form a gate electrode of the transistor;

forming a doped well in the plurality of mesas to a depth that is less than the depth of the plurality of trenches, the doped well having dopants of a second conductivity type opposite to said first conductivity type;

forming a source region inside the doped well and extending to a depth that is less than the depth of the well, the source region having dopants of the first conductivity type; and

forming a heavy body structure inside the doped well, the heavy body structure including a region having dopants of the second conductivity type with a peak concentration occurring at a predetermined depth below the depth of the source region and above the depth of the doped well.

47. The method of claim 46 further comprising forming a deep doped region having dopants of the second conductivity type, the deep doped region extending deeper than the depth of the trench.

48. The method of claim 47 wherein the step of forming a deep doped region forms a PN junction diode with the substrate that helps improve a breakdown voltage of the transistor.

49. The method of claim 47 wherein the deep doped region forms a termination structure.

50. The method of claim 46 wherein the step of substantially filling each dielectric-lined trench leaves a recess at an upper portion of each trench.

51. The method of claim 46 wherein the step of forming the heavy body structure comprises a double implant process.

52. The method of claim 51 wherein the double implant process comprises:

a first implant of dopants of the first conductivity type, at a first energy level and a first dosage to form a first doped portion of the heavy body structure; and

a second implant of dopants of the first conductivity type, at a second energy level and a second dosage to form a second doped portion of the heavy body structure.

53. The method of claim 52 wherein the first implant occurs at approximately the predetermined depth.

54. The method of claim 52 wherein the first energy level is higher than the second energy level.

55. The method of claim 54 wherein the first dosage is higher than the second dosage.

56. The method of claim 46 wherein the step of forming the heavy body structure comprises a process of diffusing dopants of the second conductivity type.

57. The method of claim 46 wherein the step of forming the heavy body structure comprises implanting dopants of the second conductivity type at about the predetermined depth.

58. The method of claim 46 wherein the step of forming a plurality of trenches comprises patterning and etching the plurality of trenches that extend in parallel along a longitudinal axis.

59. The method of claim 58 further comprising forming a contact area on the surface of the plurality of mesas.

60. The method of claim 59 wherein the step of forming the contact area comprises forming alternating source contact regions and heavy body contact regions.

61. The method of claim 59 wherein the step of forming the contact area comprises forming a ladder-shaped source contact region surrounding heavy body contact regions.

62. The method of claim 61 wherein the step of forming the ladder-shaped source contact region surrounding heavy body contact regions, comprises:

forming a source blocking mask on the surface of the plurality of mesas patterned to cover the heavy body contact regions; and

implanting dopants of the first conductivity type to form the ladder-shaped source contact region.

63. The method of claim 61 wherein the step of forming the ladder-shaped source contact region surrounding heavy body contact regions, comprises forming a dielectric layer on the surface of the plurality of mesas patterned to expose the heavy body contact regions.

64. The method of claim 46 wherein the source region is formed prior to the heavy body structure.

65. The method of claim 46 further comprising forming a drain contact region at a surface opposite to top surface of the plurality of mesas.

66. The method of claim 46 wherein the step of forming a heavy body structure forms an abrupt junction between the region having dopants of the second conductivity type and the well.

67. A method of manufacturing a trench transistor comprising:

providing a semiconductor substrate having dopants of a first conductivity type, the semiconductor substrate including a first highly doped drain layer and a second more lightly and substantially uniformly doped epitaxial layer atop and adjacent the first layer;

forming a plurality of trenches extending to a first depth into the epitaxial layer, the plurality of trenches creating a respective plurality of epitaxial mesas;

lining each of the plurality of trenches with a gate dielectric material;

substantially filling each dielectric-lined trench with conductive material;

forming a plurality of doped wells in the plurality of epitaxial mesas, respectively, to a second depth that is less than said first depth of the plurality of trenches, the plurality of doped wells having dopants of a second conductivity type opposite to said first conductivity type;

forming a plurality of source regions adjacent the plurality of trenches and inside the plurality of doped wells, the source regions having a third depth and dopants of the first conductivity type;

forming a plurality of heavy body structures each inside a respective one of the plurality of doped wells, each heavy body structure including a region having dopants of the second conductivity type with a peak concentration occurring at a predetermined depth below the depth of the source region and above the depth of the doped well,

whereby, peak electric field is moved away from a nearby trench toward the region having dopants of the second conductivity type resulting in avalanche current that is substantially uniformly distributed.

68. The method of claim 67 wherein the step of forming the plurality of heavy body structures comprises a double implant process.

69. The method of claim 68 wherein the double implant process comprises:

a first implant of dopants of the first conductivity type, at a first energy level and a first dosage to form a first doped portion of the heavy body; and

a second implant of dopants of the first conductivity type, at a second energy level and a second dosage to form a second doped portion of the heavy body.

70. The method of claim 69 wherein the first implant occurs at approximately the fourth depth.

71. The method of claim 69 wherein the first energy level is higher than the second energy level.

72. The method of claim 71 wherein the first dosage is higher than the second dosage.

73. The method of claim 67 wherein the step of forming the plurality of heavy body structures comprises implanting dopants of the second conductivity type at about the predetermined depth.