SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20070042583A1
• Filed: 08/10/2006
• Published: 02/22/2007
• Est. Priority Date: 08/16/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: JANG, Sung-Ho, LEE, Sung-Sam, KANG, Min-Sung, SONG, Sang-Ho, SHIM, Min-Young, PARK, Won-Tae
• Granted Patent: US 7,553,748 B2
• Time in Patent Office: Days
• US Class Current: 438/585
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383

Abstract

According to one embodiment, a gate structure including a gate insulation pattern, a gate pattern and a gate mask is formed on a channel region of a substrate to form a semiconductor device. A spacer is formed on a surface of the gate structure. An insulating interlayer pattern is formed on the substrate including the gate structure, and an opening is formed through the insulating interlayer pattern corresponding to an impurity region of the substrate. A conductive pattern is formed in the opening and a top surface thereof is higher than a top surface of the insulating interlayer pattern. Thus, an upper portion of the conductive pattern is protruded from the insulating interlayer pattern. A capping pattern is formed on the insulating interlayer pattern, and a sidewall of the protruded portion of the conductive pattern is covered with the capping pattern. Accordingly, the capping pattern compensates for a thickness reduction of the gate mask.

Claims

1. A semiconductor device comprising:

a substrate including impurity regions and a channel region between the impurity regions;

a gate structure including a gate insulation layer pattern, a gate pattern and a gate mask sequentially stacked on the channel region of the substrate;

a spacer on a surface of the gate structure;

an insulating interlayer pattern covering the gate structure, the insulating interlayer pattern including an opening through which at least one of the impurity regions is exposed;

a conductive pattern filled in the opening and of which a top surface is higher than a top surface of the insulating interlayer pattern, an upper portion of the conductive pattern being protruded from the insulating interlayer pattern; and

a capping layer pattern on the insulating interlayer pattern, a sidewall of the protruded upper portion of the conductive pattern being covered with the capping layer pattern.

2. The semiconductor device of claim 1, wherein a thickness ratio between the gate mask and the gate pattern is in a range of about 1:

2 to about 1;

4.

3. The semiconductor device of claim 1, wherein the spacer comprises silicon oxide.

4. The semiconductor device of claim 1, further comprising an etch stop layer interposed between the conductive pattern and the insulating interlayer pattern, and between the spacer and the insulating interlayer pattern.

5. The semiconductor device of claim 4, wherein the etch stop layer comprises silicon nitride.

6. The semiconductor device of claim 1, wherein the capping layer pattern comprises silicon nitride.

7. The semiconductor device of claim 1, wherein the capping layer pattern includes a capping spacer formed on a sidewall of the protruded upper portion of the conductive pattern and on the insulating interlayer pattern.

8. A method of manufacturing a semiconductor device, the method comprising:

providing a substrate including impurity regions and channel regions between the impurity regions;

forming, a gate structure on the channel region of the substrate, the gate structure including a gate insulation layer pattern, a gate pattern and a mask pattern sequentially stacked on the channel region of the substrate;

forming, a spacer layer covering the gate structure;

forming an insulating interlayer pattern on a resultant structure including the gate structure, the insulating interlayer pattern including a contact hole through which at least one of the impurity regions is exposed;

forming a capping layer pattern on the insulating interlayer pattern, the capping layer pattern including an opening connected to the contact hole; and

forming a conductive pattern to fill up the opening and the contact hole.

9. The method of claim 8, wherein forming the insulating interlayer pattern includes:

forming a dummy layer overlying the gate structure;

forming a dummy pattern by patterning the dummy layer in such a way that the dummy layer remains on the impurity regions, the dummy pattern extending substantially perpendicularly to the substrate in the impurity region of the substrate;

forming an insulating interlayer on the substrate including the dummy pattern to a sufficient thickness to cover the dummy pattern; and

partially removing the insulating interlayer from the substrate until a top surface of the insulating interlayer is lower than a top surface of the dummy pattern, thereby forming the insulating interlayer pattern, an upper portion of the dummy pattern being protruded from the insulating interlayer pattern.

10. The method of claim 9, wherein forming the capping layer pattern includes:

forming a capping layer on the insulating interlayer pattern to a thickness to cover the dummy pattern; and

partially removing the capping layer from the insulating interlayer pattern until a top surface of the dummy pattern is exposed.

12. The method of claim 9, wherein forming the conductive pattern includes:

forming the contact hole and the opening through which the impurity region is exposed by removing the dummy pattern and a portion of the spacer layer on the impurity region from the substrate;

forming a conductive layer on the substrate including the capping layer pattern to a thickness to fill the contact hole and the opening; and

partially removing the conductive layer from the substrate until a top surface of the capping layer pattern is exposed.

13. The method of claim 9, further comprising forming an etch stop layer on the dummy pattern and the spacer layer.

14. The method of claim 13, wherein the etch stop layer comprises silicon nitride.

15. The method of claim 9, wherein the dummy layer comprises a material having an etching selectivity with respect to the spacer layer and the insulating interlayer pattern.

16. The method of claim 15, wherein the dummy layer comprises polysilicon or silicon germanium.

17. The method of claim 8, wherein forming the gate structure comprises:

sequentially forming a gate insulation layer, a gate layer and a mask layer on the channel region;

patterning the mask layer to form the mask pattern on the gate layer; and

partially etching the gate layer and the gate insulation layer, using the mask pattern as an etch mask, to form a gate insulation layer pattern and a gate pattern on the channel region, wherein a thickness ratio between the mask layer and the gate layer is in a range of about 1;

2 to about 1;

4.

18. The method of claim 8, wherein the spacer layer comprises silicon oxide.

19. The method of claim 8, wherein the capping layer pattern comprises silicon nitride.

11. The method of claim 95 wherein forming the capping layer pattern includes:

forming a capping layer on the insulating interlayer pattern to a thickness to cover the dummy pattern; and

planarizing the capping layer until a top surface of the dummy pattern is exposed, thereby forming the capping layer pattern in such a way that a group of the dummy patterns are surrounded by the capping layer pattern at the protruded upper portion of the dummy patterns.