SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
First Claim
1. A semiconductor device comprising:
- a substrate including impurity regions and a channel region between the impurity regions;
a gate structure including a gate insulation layer pattern, a gate pattern and a gate mask sequentially stacked on the channel region of the substrate;
a spacer on a surface of the gate structure;
an insulating interlayer pattern covering the gate structure, the insulating interlayer pattern including an opening through which at least one of the impurity regions is exposed;
a conductive pattern filled in the opening and of which a top surface is higher than a top surface of the insulating interlayer pattern, an upper portion of the conductive pattern being protruded from the insulating interlayer pattern; and
a capping layer pattern on the insulating interlayer pattern, a sidewall of the protruded upper portion of the conductive pattern being covered with the capping layer pattern.
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Accused Products
Abstract
According to one embodiment, a gate structure including a gate insulation pattern, a gate pattern and a gate mask is formed on a channel region of a substrate to form a semiconductor device. A spacer is formed on a surface of the gate structure. An insulating interlayer pattern is formed on the substrate including the gate structure, and an opening is formed through the insulating interlayer pattern corresponding to an impurity region of the substrate. A conductive pattern is formed in the opening and a top surface thereof is higher than a top surface of the insulating interlayer pattern. Thus, an upper portion of the conductive pattern is protruded from the insulating interlayer pattern. A capping pattern is formed on the insulating interlayer pattern, and a sidewall of the protruded portion of the conductive pattern is covered with the capping pattern. Accordingly, the capping pattern compensates for a thickness reduction of the gate mask.
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Citations
19 Claims
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1. A semiconductor device comprising:
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a substrate including impurity regions and a channel region between the impurity regions;
a gate structure including a gate insulation layer pattern, a gate pattern and a gate mask sequentially stacked on the channel region of the substrate;
a spacer on a surface of the gate structure;
an insulating interlayer pattern covering the gate structure, the insulating interlayer pattern including an opening through which at least one of the impurity regions is exposed;
a conductive pattern filled in the opening and of which a top surface is higher than a top surface of the insulating interlayer pattern, an upper portion of the conductive pattern being protruded from the insulating interlayer pattern; and
a capping layer pattern on the insulating interlayer pattern, a sidewall of the protruded upper portion of the conductive pattern being covered with the capping layer pattern. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method of manufacturing a semiconductor device, the method comprising:
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providing a substrate including impurity regions and channel regions between the impurity regions;
forming, a gate structure on the channel region of the substrate, the gate structure including a gate insulation layer pattern, a gate pattern and a mask pattern sequentially stacked on the channel region of the substrate;
forming, a spacer layer covering the gate structure;
forming an insulating interlayer pattern on a resultant structure including the gate structure, the insulating interlayer pattern including a contact hole through which at least one of the impurity regions is exposed;
forming a capping layer pattern on the insulating interlayer pattern, the capping layer pattern including an opening connected to the contact hole; and
forming a conductive pattern to fill up the opening and the contact hole. - View Dependent Claims (9, 10, 12, 13, 14, 15, 16, 17, 18, 19)
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11. The method of claim 95 wherein forming the capping layer pattern includes:
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forming a capping layer on the insulating interlayer pattern to a thickness to cover the dummy pattern; and
planarizing the capping layer until a top surface of the dummy pattern is exposed, thereby forming the capping layer pattern in such a way that a group of the dummy patterns are surrounded by the capping layer pattern at the protruded upper portion of the dummy patterns.
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Specification