Packaging of electronic chips with air-bridge structures

• US 20070042595A1
• Filed: 10/26/2006
• Published: 02/22/2007
• Est. Priority Date: 08/25/1999
• Status: Abandoned Application

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Farrar, Paul
• Application Number:
  US11/586,876
• Publication Number:
  US 20070042595A1
• Time in Patent Office: Days
• US Class Current: 438/617
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 23/20 gaseous at the normal operating temperature of the device
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/4821 Bridge structure with air gap
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/1433 Application-specific integrated circuit [ASIC]
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

A circuit assembly for fabricating an air bridge structure and a method of fabricating an integrated circuit package capable of supporting a circuit assembly including an air bridge structure. A circuit assembly comprises an electronic chip and a conductive structure embedded in a plurality of materials having a plurality of vaporization temperatures. The plurality of materials is formed on the electronic chip and the conductive structure is coupled to the electronic chip. To fabricate the circuit assembly, a support structure, including interstices, is formed on an electronic chip. The interstices of the support structure are filled with a material having a vaporization temperature that is less than the vaporization temperature of the support structure. Conductive structures are embedded in the support structure and the material, and a connective structure is mounted on the support structure. Finally, the material is removed from the interstices by heating the circuit assembly.

Claims

1. A method of forming an air bridge structure comprising:

forming a material layer on an electronic chip;

embedding a conductive support structure and at least one conductive structure in the material layer, the at least one conducive structure including a horizontal interconnect path coupled to at least two vertical wirings coupled to the electronic chip; and

removing the material layer.

2. The method of claim 1, wherein embedding a conductive support structure and at least one conductive structure in the material layer comprises:

etching the material layer to form a plurality of vertical wiring vias and a plurality of vertical support vias;

etching a wiring pattern including the horizontal interconnect path in the material layer; and

applying a conductive material to the plurality of vertical wiring vias, the plurality of vertical support vias, and the wiring pattern.

3. The method of claim 1, wherein removing the material layer comprises:

vaporizing the material layer.

4. The method of claim 3, wherein vaporizing the material layer comprises:

processing the integrated circuit assembly in a furnace having an oxygen atmosphere at a temperature of approximately 400 degrees centigrade.

5. A method of forming an air bridge structure comprising:

forming a material layer on an electronic chip;

embedding a conductive support structure and at least one conductive structure in the material layer, the at least one conducive structure including a horizontal interconnect path coupled to at least two vertical wirings coupled to the electronic chip

mounting a connective structure on the conductive support structure; and

removing the layer material.

6. The method of claim 5, further comprising:

attaching a heat sink to the electronic chip.

7. A method of packaging an integrated circuit comprising:

fabricating an integrated circuit structure including a conductive structure and a post support structure embedded in a fill material including a polymer;

mounting C4 pads on the integrated circuit structure;

mounting the integrated circuit structure on a substrate;

removing the fill material; and

backfilling with a gas and hermetically sealing the substrate.

8. The method of claim 7, wherein fabricating the conductive structure and the post support structure includes fabricating the conducive structure and the post support structure at a same time.

9. The method of claim 7, wherein the post support structure includes at least one post formed as a conductive post.

10. The method of claim 9, wherein the at least one post formed as a conducive post is formed from a same conductive material used to form the conductive structure.

11. The method of claim 9, wherein the at least one post formed as a conductive post is terminated in an insulator at a surface of the integrated circuit structure.

12. The method of claim 7, wherein the fill material is a high temperature polymer.

13. The method of claim 12, wherein the high temperature polymer is polyimide.

14. The method of claim 7, where the conductive structure includes copper.

15. The method of claim 7, wherein the conducive structure includes gold.

16. The method of claim 7, wherein the post support structure includes copper.

17. The method of claim 7, wherein the post support structure includes an alloy of copper.

18. A method of constructing an integrated circuit comprising:

fabricating a plurality of electronic devices on a substrate;

embedding a wiring structure in a plurality of materials having a plurality of vaporization temperatures, the plurality of materials including a fill material including a polymer, the plurality of materials is located on the substrate and the wiring structure interconnects the plurality of electronic devices;

mounting the integrated circuit on a packaging substrate; and

removing at least one of the plurality of materials after the integrated circuit is mounted on the packaging substrate.

19. The method of claim 18, further comprising:

attaching a C4 structure to the integrated circuit prior to mounting the integrated circuit on the packaging substrate.

20. The method of claim 18, wherein removing at least one of the plurality of materials after the integrated circuit is mounted on the packaging substrate comprises:

heating the integrated circuit.

21. The method of claim 18, wherein removing at least one of the plurality of material after the integrated circuit is mounted on th packaging substrate including using an oxygen plasma.

22. A method comprising:

fabricating a layer of material including a polymer above an electronic chip;

patterning and etching the layer of material to form a template for at least one level including a horizontal interconnect path coupling two or more of a plurality of vertical wiring vias coupled to the electronic chip and at least one support post;

filling the template with a conductive material to form at least one horizontal interconnect path, wherein the at least one horizontal interconnect path is coupled to two of more of the plurality of vertical wiring vias and is supported by the at least one support post;

planarizing the conductive material back to a surface of the layer of material;

fabricating an insulative layer above layer of material;

patterning and etching the insulative layer to form via sites;

filling the via sites with the conductive material to form C4 contacts;

etching an opening in the insulative layer to the layer of material;

reflowing the C4 contacts in a hydrogen atmosphere;

joining the C4 contacts to a substrate in the hydrogen atmosphere; and

removing the layer of material using an oxygen plasma.

23. The method of claim 22, including fabricating more than one level of horizontal interconnect paths.

24. The method of claim 22, the at least one support post is formed on an insulative layer on a surface of the electronic chip.

25. The method of claim 22, wherein filling the via sites includes each of the via sites coupled to one of the at least one horizontal interconnect path.

26. The method of claim 22, wherein filling the template with conductive material includes filling the template with conducive material including copper.