Receiver ADC clock delay based on echo signals

• US 20070042721A1
• Filed: 08/17/2005
• Published: 02/22/2007
• Est. Priority Date: 08/17/2005
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Teranetics, Inc. (Broadcom, Inc.)
• Inventors: Tellado, Jose, Gupta, Sandeep
• Granted Patent: US 7,720,015 B2
• Time in Patent Office: Days
• US Class Current: 455/73
• CPC Class Codes: H04B 3/23 using a replica of transmitted signal in the time domain, e.g. echo cancellers

Abstract

A device and method for a full-duplex transceiver is disclosed. The transceiver includes a transmitter DAC coupled to a transmission channel. The transmit DAC converting a digital transmission signal into an analog transmission signal. The transceiver further includes a receiver connected to the transmission channel. The receiver receives a desired signal and an echo signal, in which the echo signal includes at least a portion of the analog transmission signal. The receiver includes a receiver ADC, a programmable delay line for adjustably delaying a clock signal of the ADC, and a receiver processing circuit for adjusting the delay of the clock signal based at least in part upon the echo signal.

Claims

1. A full-duplex transceiver comprising:

a transmitter DAC coupled to a transmission channel, the transmit DAC converting a digital transmission signal into an analog transmission signal;

a receiver connected to the transmission channel, the receiver receiving a desired signal, and an echo signal comprising at least a portion of the analog transmission signal, the receiver comprising;

a receiver ADC;

a programmable delay line for adjustably delaying a clock signal of the receiver ADC;

receiver processing circuit for adjusting the delay of the clock signal based at least in part upon the echo signal.

2. The transceiver of claim 1, wherein the receiver processing circuit comprises a DSP circuit for controlling the programmable delay line so that sampling of the receiver ADC provides an optimal range of echo signal cancellation.

3. The transceiver of claim 1, wherein the delay of the clock signal is adjusted so that sampling of the ADC occurs when the echo signal is below a threshold.

4. The transceiver of claim 1, wherein the delay of the clock signal is adjusted so that receiver ADC sampling occurs when linearity of the echo signal is above a threshold, noise in the echo signal due to jitter of the clock the transmitter DAC is below a threshold, and an amount of echo signal sampled by the receiver ADC is below a threshold.

5. The transceiver of claim 1, wherein the delay of the clock signal is adjusted so that sampling of the receiver ADC occurs when linearity of the echo signal is above a threshold.

6. The transceiver of claim 1, wherein the delay of the clock signal is adjusted so that sampling of the receiver ADC occurs when noise in the echo signal due to jitter of the clock of the transmitter DAC is below a threshold.

7. The transceiver of claim 1, wherein the delay of the clock signal is adjusted until a processed received signal provides a threshold level of bit error rate (BER) or signal to noise ratio (SNR).

8. The transceiver of claim 1, wherein the delay of the clock signal is adjusted until a processed received signal provides a threshold level of Decision Point Mean Square Error (DPMSE).

9. The transceiver of claim 1, wherein the delay of the clock signal is adjusted until a processed received signal provides an optimal bit error rate (BER) or signal to noise ratio (SNR).

10. The transceiver of claim 1, wherein the delay of the clock signal is adjusted until a processed received signal provides a minimum Decision Point Mean Square Error (DPMSE).

11. The transceiver of claim 1, wherein the delay of the clock signal is adjusted until echo cancellation of a processed received signal provides a threshold level of a decision point peak error rate (DPPER).

12. The transceiver of claim 1, wherein the delay of the clock signal is adjusted so that after echo signal cancellation, a post-processed decision point error is below a threshold.

13. The transceiver of claim 12, wherein the post-processed decision point error comprises at least one of a mean error, a peak error or a probability density function error.

14. The transceiver of claim 12, wherein the post-processed decision point error is transformed to a frequency domain, and the frequency domain error comprises at least one of a mean error, a peak error or a probability density function error.

15. The transceiver of claim 1, further comprising:

a summer circuit coupled to the input of the receiver, for summing the desired signal and the echo signal with an estimated echo signal to provide cancellation of the echo signal previous to the receiver ADC.

16. The transceiver of claim 15, wherein the summer circuit comprises:

an amplifier having a virtual ground node;

a feed back circuit from an output of the amplifier to the virtual ground node;

an adjustable echo cancellation DAC, an output of the echo cancellation DAC being summed at the virtual ground node, the adjustable echo cancellation DAC being adjusted according to an estimated echo signal.

17. The transceiver of claim 15, further comprising an EC delay circuit for delaying an echo cancellation DAC clock signal with respect to the receiver DAC.

18. The transceiver of claim 17, further comprising a delay of the EC delay circuit being programmably controlled by the receiver processing circuit.

19. The transceiver of claim 17, wherein a delay of the EC delay circuit is fixed.

20. The transceiver of claim 17, wherein the receiver processing circuit controls the delay of the EC delay circuit to enhance echo signal cancellation provided by the echo cancellation DAC.

21. The transceiver of claim 17, wherein the receiver processing circuit controls the delay of the EC delay circuit to optimize an EC DAC preprocessor signal.

22. The transceiver of claim 21, wherein the EC DAC preprocessor is a digital filter.

23. The transceiver of claim 22, wherein the EC DAC preprocessor is optimized when the signal energy of coefficients of the digital filter is focused on a single coefficient.

24. A method of echo signal cancellation within a transceiver, comprising:

a transmitter DAC transmitting an analog transmission signal on a transmission channel, the transmitter DAC being clocked with transmit DAC clock signal;

receiving a desired signal, and an echo signal comprising at least a portion of the analog transmission signal;

digitally sampling the desired signal and the echo signal with a receiver ADC; and

adjustably delaying a clock signal of the ADC, the delay being adjusted at least in part upon the echo signal.

25. The method of claim 24, further comprising the delay of the ADC clock signal being adjusted so that the ADC sampling occurs where linearity of the echo signal is above a threshold.

26. The method of claim 24, further comprising the delay ADC clock signal being adjusted so that the ADC sampling occurs when noise of a sampled echo signal due to jitter of the transmitter DAC clock signal is below a threshold.

27. The method of claim 24, further comprising the delay ADC clock signal being adjusted so that the ADC sampling occurs when an amount of echo signal sampled by the receiver ADC is below a threshold.

28. The method of claim 24, further comprising the delay being adjusted so that the ADC sampling occurs where the linearity of the echo signal is above a threshold, and noise of a sampled echo signal due to jitter of the transmitter DAC clock signal is below a threshold, and an amount of echo signal sampled by the receiver ADC is below a threshold.

29. A method of echo signal cancellation within a transceiver, comprising:

a transmitter DAC transmitting an analog transmission signal on a transmission channel, the transmitter DAC being clocked with transmit DAC clock signal;

receiving a desired signal, and an echo signal comprising at least a portion of the analog transmission signal;

summing the desired signal and the echo signal with an estimated echo signal, producing the desired signal and a residual echo signal;

sampling the desired signal and the residual echo signal with a receiver ADC;

adjustably delaying a clock signal of the ADC, the delay being adjusted at least in part upon the echo signal;

processing digital samples of the ADC further canceling the residual echo signal.

30. The method of claim 29, further comprising the delay being adjusted so that the ADC sampling occurs when linearity of the echo signal is above a threshold.

31. The method of claim 29, further comprising the delay being adjusted so that the ADC sampling occurs when noise of a sampled echo signal due to jitter of the transmitter DAC is below a threshold.

32. The method of claim 29, further comprising the delay ADC clock signal being adjusted so that the ADC sampling occurs when an amount of echo signal sampled by the receiver ADC is below a threshold.

33. The method of claim 29, further comprising the delay being adjusted so that the ADC sampling occurs where the linearity of the echo signal is above a threshold, and noise of a sampled echo signal due to jitter of the transmitter DAC clock signal is below a threshold, and an amount of echo signal sampled by the receiver ADC is below a threshold.

34. The method of claim 29, further comprising adjustably delaying a phase of the estimated echo signal.

35. The method of claim 34, wherein the phase of the estimated echo signal is adjusted by adjusting a delay of a clock signal of an EC DAC of the estimated echo signal.