Half-duplex communication system, low-voltage differential signaling transceiver of the system and pre-driver of the transceiver

• US 20070042722A1
• Filed: 06/20/2006
• Published: 02/22/2007
• Est. Priority Date: 06/21/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Jin
• Granted Patent: US 7,504,863 B2
• Time in Patent Office: Days
• US Class Current: 455/73
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/028 Arrangements specific to the transmitter end
• CPC Class Codes: H04L 25/0284 Arrangements to ensure DC-balance
• CPC Class Codes: H04L 5/16 Half-duplex systems; Simplex/duplex switching; Transmission of break signals non-automatically inverting the direction of transmission

Abstract

A half-duplex communication system may include one or more low-voltage differential signaling half-duplex transceivers. Each transceiver may include a plurality of input terminals receiving a plurality differential data signals, an input driver transferring the differential data signals from differential transmission lines through output terminals, and an output driver transferring the differential data signals from the input terminals through the differential transmission lines and out to one of the first and second transceivers via the non-inverse and inverse transmission lines. The differential data signals may be transferred in response to the differential data signals at the input terminals and at the output terminals of the input driver. Each transceiver may include a pre-driver configured to shift a reference voltage level of differential data signals input thereto from the input terminals and which are to be supplied to the output driver therefrom.

Claims

1. A low-voltage differential signaling transceiver, comprising:

a plurality of input terminals receiving a plurality of differential data signals;

an input driver transferring the differential data signals from one or more differential transmission lines through a plurality of output terminals; and

an output driver transferring the differential data signals from the input terminals through the differential transmission lines in response to the differential data signals at the input terminals and at the output terminals of the input driver.

2. The transceiver of claim 1, wherein the output driver includes:

a pair of first channel transistors regulating currents on the differential transmission lines in response to differential data signals received from a corresponding input terminals, and

a pair of second channel transistors regulating the currents on the differential transmission lines in response to differential data signals returning thereto via a feedback loop.

3. The transceiver of claim 2, wherein

the input driver includes a current-mode differential amplifier driven in a high potential region, and

the pair of second channel transistors are PMOS transistors.

4. The transceiver of claim 2, wherein the input driver includes:

a third pair of transistors driven in a high potential region in response to the differential data signals on the differential transmission so as to regulate the current on the differential transmission line, and

a fourth pair of transistors driven in a low potential region in response to the differential data signals on the differential transmission so as to regulate the current on the differential transmission lines, and

wherein the pair of second channel transistors are PMOS transistors.

5. The transceiver of claim 2, wherein

the input driver includes a current-mode differential amplifier driven in a low potential region, and

the pair of second channel transistors are NMOS transistors.

6. The transceiver of claim 1, further comprising:

a pre-driver shifting a reference voltage level of the differential data signals to be supplied to the output driver from the input terminals, wherein

the pre-driver is connected between the input terminals and the output driver.

7. The transceiver of claim 6, wherein the output driver includes:

a pair of first channel transistors regulating currents on the differential transmission lines in response to corresponding differential data signals received from the pre-driver, and

a pair of second channel transistors regulating the currents on the differential transmission lines in response to differential data signals returning thereto via a feedback loop.

8. The low-voltage differential signaling transceiver as set forth in claim 7, wherein

the pre-driver includes a current-mode differential amplifier driven in a low potential region, and

the pair of first channel transistors are NMOS transistors.

9. The transceiver of claim 7, wherein

the pre-driver includes a current-mode differential amplifier driven in a high potential region, and

the pair of first channel transistors are PMOS transistors.

10. The transceiver of claim 1, wherein the feedback loop is configured to return the differential data signals of the differential transmission lines toward the output driver, the returning differential data signals having the same phases as the differential data signals at the input terminals.

11. A pre-driver for a low-voltage differential signaling transceiver, the transceiver having a plurality of input terminals receiving differential data signals and an output driver, the pre-driver comprising:

a first transistor connected between a first input terminal and the output driver, the first transistor regulating an amount of current flowing from a first output node connected thereto to a sink node connected thereto based on a potential of a differential data signal on a first input line connected to the first transistor from the first input terminal, and

a second transistor connected between a second input terminal and the output driver, the second transistor regulating an amount of current flowing from a second output node connected thereto to the sink node based on a potential of a differential data signal on a second input line connected to the second transistor from the second input terminal.

12. The pre-driver of claim 11, wherein the first and second transistors are NMOS transistors.

13. The pre-driver of claim 11, wherein the first and second transistors shift a reference voltage level of the differential data signals input thereto and to be supplied to the output driver from the input terminals.

14. The pre-driver of claim 11, wherein the first and second transistors amplify a gap signal between differential data signals on the first and second input lines, and supply the amplified gap signal to the output driver.

15. The pre-driver of claim 11, wherein

the differential data signal on the first input line is a non-inverse data signal, and

the first transistor allows more current to flow from the first output mode to the sink node if the non-inverse data signal on the first input line is set to a high potential, so as to cause a low-potential data signal to appear at the first output node, else

if the non-inverse data signal on the first input line is set to a low potential, the first transistor permits less current to flow from the first output node to the sink node so as to cause a high-potential data signal to appear at the first output node.

16. The pre-driver of claim 11, wherein

the differential data signal on the second input line is an inverse data signal, and

the second transistor allows less current to flow from the second output mode to the sink node if the inverse data signal on the second input line is set to a high potential, so as to cause a low-potential data signal to appear at the first output node, else

if the inverse data signal on the second input line is set to a high potential, the second transistor permits more current to flow from the second output node to the sink node so as to cause a high-potential data signal to appear at the second output node.

17. The pre-driver of claim 11, further comprising:

a first resistor connected between the first output node and a high-potential power source, and

a second resistor connected between the second output node and the high-potential power source,

wherein the first and second resistors are used as loads on the first and second transistors.

18. The pre-driver of claim 11, further comprising:

a third transistor functioning as a current sink to regulate the amount of current flowing through the sink node.

19. The pre-driver of claim 18, wherein the third transistor is an NMOS transistor configured to regulate the amount of current flowing from the sink node toward a low-potential power source based on a potential level of a bias voltage signal applied as an input thereto.

20. The pre-driver of claim 18, wherein the pre-driver includes only three NMOS transistors and further includes a pair of resistors for providing loads on the first and second transistors.

21. A half-duplex communication system, comprising:

a first transceiver, and

a second transceiver connected to the first transceiver via a non-inverse transmission line and an inverse transmission line, wherein each transceiver includes;

a plurality of input terminals receiving a plurality of differential data signals,

an input driver transferring the differential data signals from differential transmission lines through output terminals,

an output driver transferring the differential data signals from the input terminals through the differential transmission lines and out to one of the first and second transceivers via the non-inverse and inverse transmission lines, in response to the differential data signals at the input terminals and at the output terminals of the input driver, and

a pre-driver configured to shift a reference voltage level of differential data signals input thereto from the input terminals and to be supplied to the output driver therefrom.