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Random number generator

  • US 20070043798A1
  • Filed: 08/16/2005
  • Published: 02/22/2007
  • Est. Priority Date: 08/16/2005
  • Status: Active Grant
First Claim
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1. A random number generator within a processor, comprising:

  • an array of oscillators, wherein each oscillator operates at a different frequency;

    an array of latches, wherein each latch receives an input from a separate oscillator, receives a sample signal, and produces an output signal of the oscillator in response to the sample signal; and

    random number determination logic (“

    RNDL”

    ), wherein the RNDL is at least configured to receive the output signals of the array of latches and generate a random number seed.

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