Random number generator

• US 20070043798A1
• Filed: 08/16/2005
• Published: 02/22/2007
• Est. Priority Date: 08/16/2005
• Status: Active Grant

• Current Assignee: Diana R. Gerhardt
• Original Assignee: Diana R. Gerhardt
• Inventors: Hailu, Eskinder, Liberty, John, Boerstler, David, Hofstee, Harm
• Granted Patent: US 7,890,561 B2
• Time in Patent Office: Days
• US Class Current: 708/251
• CPC Class Codes: G06F 7/588 Random number generators, i.e. based on natural stochastic processes
• CPC Class Codes: H04L 9/001 using chaotic signals
• CPC Class Codes: H04L 9/0869 involving random numbers or seeds

Abstract

A random number generator, a method, and a computer program product are provided for producing a random number seed. Each oscillator within an array of oscillators operates at a different frequency. The operating frequencies of each oscillator are not harmonically related, such that no integer multiple exists between the frequencies of any two oscillators. In one embodiment, the outputs of the array of oscillators connect to a multiple input latch. The multiple input latch also receives a sample signal, which is a clock signal. The clock signal samples the outputs of the array of oscillators, and the multiple input latch in conjunction with the random number determination logic (“RNDL”) produces a digital output (0 or 1) for each oscillator within the array. The RNDL uses these digital outputs to create a random number seed.

Claims

1. A random number generator within a processor, comprising:

an array of oscillators, wherein each oscillator operates at a different frequency;

an array of latches, wherein each latch receives an input from a separate oscillator, receives a sample signal, and produces an output signal of the oscillator in response to the sample signal; and

random number determination logic (“

RNDL”

), wherein the RNDL is at least configured to receive the output signals of the array of latches and generate a random number seed.

2. The random number generator of claim 1, wherein the random number generator is used in a computer system or a data processing system.

3. The random number generator of claim 1, wherein the array of oscillators comprise a plurality of multistage free-running ring oscillators.

4. The random number generator of claim 1, wherein the operating frequencies of each oscillator are not harmonically related, such that no integer multiple exists between the frequencies of any two oscillators.

5. The random number generator of claim 1, wherein the array of latches further comprise one multiple input latch or one multiple input flip-flop coupled to the array of oscillators, that is at least configured to produce an output signal for each oscillator within the array.

6. The random number generator of claim 1, wherein in the array of latches further comprise an array of flip-flops coupled to the array of oscillators.

7. The random number generator of claim 1, wherein the sample signal is a clock signal that samples the output signals from the array of oscillators.

8. The random number generator of claim 1, wherein the RNDL is at least configured to:

read a digital output (0'"'"'s or 1'"'"'s) from each latch of the array of latches; and

produce a random number seed containing those digital outputs.

9. The RNDL of claim 8, wherein the RNDL is at least configured to transmit the random number seed to other areas of the processor.

10. A method, in a processor, for producing a random number seed, comprising:

configuring an array of oscillators so that each oscillator operates at a different frequency;

coupling an array of latches to the array of oscillators so that each latch is coupled to a separate oscillator;

generating a sample signal;

transmitting the sample signal to the array of latches;

in response to the sample signal, generating output signals from the array of oscillators;

producing a random number seed from the output signals of the array of oscillators.

11. The method of claim 10, wherein the method is used in a computer system or a data processing system.

12. The method of claim 10, wherein the array of oscillators comprise a plurality of multistage free-running oscillators.

13. The method of claim 10, wherein the operating frequencies of each oscillator are not harmonically related, such that no integer multiple exists between the frequencies of any two oscillators.

14. The method of claim 10, wherein the array of latches further comprise one multiple input latch or one multiple input flip-flop coupled to the array of oscillators, that is at least configured to produce an output signal for each oscillator within the array.

15. The method of claim 10, wherein the array of latches further comprise an array of flip-flops coupled to the array of oscillators.

16. The method of claim 10, wherein the step of generating a sample signal further comprises generating a clock signal designed to sample the output signals from the array of oscillators.

17. The method of claim 10, wherein the step of generating output signals in response to the sample signal further comprises configuring the array of latches so that they produce digital outputs (0'"'"'s and 1'"'"'s) of the signals from the array of oscillators in response to the sample signal.

18. The method of claim 10, wherein the step of generating a random number seed further comprises:

reading a digital output (0'"'"'s or 1'"'"'s) from each latch of the array of latches; and

producing a random number seed containing those digital outputs.

19. The method of claim 18, wherein producing the random number seed further comprises transmitting the random number seed to other areas of the processor.

20. A computer program product for producing a random number seed, with the computer program product having a medium with a computer program embodied thereon, wherein the computer program comprises:

computer code for configuring an array of oscillators so that each oscillator operates at a different frequency;

computer code for coupling an array of latches to the array of oscillators so that each latch is coupled to a separate oscillator;

computer code for generating a sample signal;

computer code for transmitting the sample signal to the array of latches;

in response to the sample signal, computer code for generating output signals from the array of oscillators;

computer code for producing a random number seed from the output signals of the array of oscillators.