INTEGRATED CIRCUIT FOR THE PROCESSING AND SUBSEQUENT ROUTING OF MOTION PICTURE EXPERT GROUP (MPEG) DATA BETWEEN INTERFACES

• US 20070043892A1
• Filed: 01/22/2004
• Published: 02/22/2007
• Est. Priority Date: 01/22/2004
• Status: Abandoned Application

• Current Assignee: Semiconductores Investigacion y Diseno SA
• Original Assignee: Semiconductores Investigacion y Diseno SA
• Inventors: ISENSER FARRE, Jose
• Application Number:
  US10/596,806
• Publication Number:
  US 20070043892A1
• Time in Patent Office: Days
• US Class Current: 710/100
• CPC Class Codes: H04N 21/2365 Multiplexing of several video streams
• CPC Class Codes: H04N 21/4147 PVR [Personal Video Recorder] H04N5/76 takes precedence ; arrangements for broadcast with accumulation-type receivers H04H20/40
• CPC Class Codes: H04N 21/4181 for conditional access
• CPC Class Codes: H04N 21/426 Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/42607 for processing the incoming bitstream
• CPC Class Codes: H04N 21/42661 for reading from or writing on a magnetic storage medium, e.g. hard disk drive
• CPC Class Codes: H04N 21/4347 Demultiplexing of several video streams
• CPC Class Codes: H04N 21/43615 Interfacing a Home Network, e.g. for connecting the client to a plurality of peripherals home Audio Video Interoperability [HAVI] data switching networks H04L12/2805

Abstract

The invention relates to a circuit which is integrated in a receiver system for digital television networks and which processes and routes data from one or more Motion Picture Expert Group (MPEG) data streams between two or more interfaces or peripherals, using an embedded processor (PROC) and an internal shared bus (BUS). The inventive integrated circuit comprises at the least the following integrated peripherals: two input MPEG stream interfaces (ITSINA and ITSINB); two output MPEG stream interfaces (ITSOUTA and ITSOUTB); a hard disk interface (IHD); a local network interface (ILAN); two smart card interfaces (ISMCA and ISMCB); a generic master interface to external slave peripherals and external memory (IMB); and a generic slave interface from another external master device (ISB).

Claims

1. - Circuit integrated in a receiver system for digital television networks, characterized by the fact that it can process the flow of data from one or several MPEG data streams with different functions so that it adapts to receiver applications and to multimedia information servers (video, audio and data).

2. - The circuit that constitutes this invention is characterized by its versatility since it incorporates a single internal bus structure in which the transactions may be originated by the processor embedded into the circuit or by the peripherals.

3. - In addition, the circuit that constitutes this invention is characterized by the fact that it incorporates subsystems with routing and processing functions implemented by hardware and software, and used as modules that comprise the possible circuit configurations.

4. - The invention is characterized by a specific switching function between two or more conditional access systems. Even though it has been described for the case of 2 conditional accesses over 2 independent data streams, the current claim can be extrapolated to any number of conditional accesses and data screams.

5. - The invention is characterized by the fact that is it easily configurable, allowing at least the following functionalities:

1—

Processing of two input data streams to two output data streams;

2—

Processing of one input data stream (ITSINB) and one internally-synthesized data stream from the processor (PROC) to two output data streams;

3—

Processing of one input data stream (ITSINB), and one data stream from a local network access (ILAN), to two output data streams;

4—

Processing of two data streams, both from a local network connection (ILAN), to two output data streams; and

5—

Processing of two input data streams (ITSINA and ITSINB) to a local network concentrator/multiplexor.