SYMMETRIC MULTIPROCESSOR OPERATING SYSTEM FOR EXECUTION ON NON-INDEPENDENT LIGHTWEIGHT THREAD CONTEXTS

• US 20070043935A2
• Filed: 01/11/2006
• Published: 02/22/2007
• Est. Priority Date: 08/28/2003
• Status: Active Grant

• Current Assignee: MIPS Tech, LLC
• Original Assignee: MIPS Technologies Incorporated (Wave Computing, Inc.)
• Inventors: Kissell, Kevin
• Granted Patent: US 7,418,585 B2
• Time in Patent Office: Days
• US Class Current: 712/228
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/3009 Thread control instructions
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/455 Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A multiprocessing system is disclosed. The system includes a multithreading microprocessor including a plurality of thread contexts (TCs), each having a program counter and a general purpose register set for executing a thread. The microprocessor also includes a shared privileged resource, shared by the plurality of TCs rather than being replicated for each of the plurality of TCs, and privileged to be managed only by operating system-privileged threads rather than by user-privileged threads. The system also includes a multiprocessor operating system (OS), configured to manage the shared privileged resource, and to schedule execution of both the operating system-privileged threads and the user-privileged threads on the plurality of TCs.

Claims

1. A multiprocessing system, comprising:

a multithreading microprocessor, comprising;

a plurality of thread contexts (TCs), each having a program counter and a general purpose register set for executing a thread; and

a shared privileged resource, shared by said plurality of TCs rather than being replicated for each of said plurality of TCs, and privileged to be managed only by operating system-privileged threads rather than by user-privileged threads; and

a multiprocessor operating system (OS), configured to manage said shared privileged resource, and to schedule execution of both said operating system-privileged threads and said user-privileged threads on said plurality of TCs.

2. The system as recited in claim 1, wherein said shared privileged resource comprises a translation lookaside buffer (TLB).

3. The system as recited in claim 2, wherein said microprocessor further comprises interrupt control logic shared by said plurality of TCs rather than being replicated for each of said plurality of TCs, and privileged to be managed only by operating system-privileged threads rather than by user-privileged threads, wherein said OS is further configured to manage said interrupt control logic.

4. The system as recited in claim 1, wherein said microprocessor further comprises:

a second plurality of thread contexts (TCs), each having a program counter and a general purpose register set for executing a thread; and

a second shared privileged resource, shared only by said second plurality of TCs, and rather than being replicated for each of said second plurality of TCs, and privileged to be managed only by said operating system-privileged threads rather than by said user-privileged threads.

5. The system as recited in claim 4, wherein each of said first and second shared privileged resource comprises an exception domain.

6. The system as recited in claim 5, wherein said microprocessor further comprises a translation lookaside buffer (TLB) shared by said first and second plurality of TCs rather than being replicated for each of said first and second plurality of TCs, and privileged to be managed only by said operating system-privileged threads rather than by said user-privileged threads, wherein said OS is further configured to manage said TLB.

7. The system as recited in claim 4, wherein each of said first and second shared privileged resource comprises a TLB.

8. The system as recited in claim 1, wherein said shared privileged resource comprises an exception domain.

9. The system as recited in claim 8, wherein said exception domain comprises a control register programmable by said OS for controlling enablement and disablement of interrupt requests globally to all of said plurality of TCs.

10. The system as recited in claim 8, wherein said exception domain comprises a status register readable by said OS for determining a source of interrupt requests, wherein said interrupt requests are non-specific to said plurality of TCs, wherein said exception domain is configured to select one of said plurality of TCs to execute a thread to service an active one of said interrupt requests.

11. The system as recited in claim 8, wherein said OS is configured execute a thread on a first of said plurality of TCs for directing an exception to a second of said plurality of TCs by writing an address of an interrupt handler to said program counter of said second of said plurality of TCs.

12. The system as recited in claim 11, wherein each of said plurality of TCs further comprises a control indicator for controlling whether said TC is halted from execution, wherein said thread executing on said first of said plurality of TCs is further configured to write to said control indicator of said second of said plurality of TCs to halt execution of a second thread executing thereon, prior to said writing said address of said interrupt handler to said program counter of said second of said plurality of TCs.

13. The system as recited in claim 12, wherein said thread executing on said first of said plurality of TCs is further configured to write to said control indicator of said second of said plurality of TCs to commence execution of said interrupt handler on said second of said plurality of TCs, after said writing said address of said interrupt handler to said program counter of said second of said plurality of TCs.

14. The system as recited in claim 8, wherein said microprocessor further comprises a translation lookaside buffer (TLB) shared by said plurality of TCs rather than being replicated for each of said plurality of TCs, and privileged to be managed only by operating system-privileged threads rather than by user-privileged threads, wherein said OS is further configured to manage said TLB.

15. The system as recited in claim 1, wherein said OS comprises a data structure having an entry for each of said plurality of TCs, each said entry containing information describing capabilities of said corresponding one of said plurality of TCs, wherein each said entry further comprises a TC identifier field for identifying a corresponding one of said plurality of TCs, wherein said OS is further configured to populate said TC identifier field for each of said entries with a unique identifier value.

16. The system as recited in claim 15, wherein said unique identifier value is stored in a MIPS Multithreading Application Specific Extension (MT ASE) current thread context (CurTC) field in a TCBind Register.

17. The system as recited in claim 15, wherein said OS is configured to invoke a CPU probe routine only for a first of said plurality of TCs, and in response, to populate said first entry with information describing said shared privileged resource, and to subsequently copy said first entry to each remaining entry of said data structure without invoking said CPU probe routine for said remaining plurality of TCs.

18. The system as recited in claim 15, wherein said multithreading microprocessor further comprises:

one or more virtual processing elements (VPEs), wherein each of said one or more VPEs is an exception domain for a mutually exclusive subset of one or more of said plurality of TCs;

wherein each said entry further comprises a VPE identifier field for identifying one of said VPEs bound to said corresponding one of said plurality of TCs;

wherein said OS is further configured to populate said VPE identifier field for each of said entries with an identifier value identifying one of said VPEs to which said corresponding one of said plurality of TCs is bound.

19. The system as recited in claim 18, wherein said unique identifier value is stored in a MIPS Multithreading Application Specific Extension (MT ASE) current VPE (CurVPE) field in a TCBind Register.

20. The system as recited in claim 18, wherein said OS is configured to invoke a per-CPU trap initialization routine only for one of said subset of TCs per one of said VPEs.

21. The system as recited in claim 1, wherein said plurality of TCs is configured as an array of thread contexts (TCs), wherein each of said plurality of TCs further comprises a register for storing an index of said respective TC within said array, wherein said OS is further configured to maintain a table of entries, each said entry for storing a CPU-unique value for a respective one of said TCs, wherein said OS comprises a respective thread configured to execute on each of said respective TCs and to read said index from said register of said respective one of said TCs and to read said respective CPU-unique value for said respective one of said TCs using said index.

22. The system as recited in claim 21, wherein said CPU-unique value comprises a kernel stack pointer.

23. The system as recited in claim 21, wherein said CPU-unique value comprises a page table origin.

24. The system as recited in claim 21, wherein said shared privileged resource comprises a register for indicating which of a plurality of interrupt requests is active, wherein said CPU-unique value comprises a storage location for saving and restoring said contents of said register indicating which of a plurality of interrupt requests is active.

25. The system as recited in claim 21, wherein said thread is further configured to shift said index value a predetermined number of bits and add said shifted index value to a base address of said table to obtain an address from which to read said respective CPU-unique value for said one of said TCs.

26. The system as recited in claim 1, wherein said OS comprises program instructions configured to cause each of said plurality of TCs to execute an instance of said OS, wherein each of said instances of said OS is configured to schedule execution of said operating system-privileged threads on said plurality of TCs to manage said shared privileged resource and to schedule execution of said user-privileged threads on said plurality of TCs.

27. The system as recited in claim 1, wherein said multithreading microprocessor further comprises:

an instruction scheduler, coupled to said plurality of TCs, configured to dispatch to execution units, in a multithreaded fashion, instructions of both said operating system-privileged and said user-privileged threads executing on said plurality of TCs.

28. A method for a multiprocessor operating system (OS) to run on a multiprocessing system having a multithreading microprocessor including a plurality of thread contexts (TCs) each having a program counter and a general purpose register set for executing a thread, and a shared privileged resource shared by the plurality of TCs rather than being replicated for each of the plurality of TCs, the method comprising:

managing the shared privileged resource only by operating system-privileged threads of the OS executing on all of the plurality of TCs rather than by user-privileged threads executing on each of the plurality of TCs; and

scheduling execution of both the operating system-privileged threads and the user-privileged threads on the plurality of TCs.

29. The method as recited in claim 28, wherein the shared privileged resource comprises a translation lookaside buffer (TLB).

30. The method as recited in claim 29, wherein said managing the TLB comprises filling a missing entry in the TLB in response to a miss in the TLB.

31. The method as recited in claim 28, wherein the microprocessor further comprises interrupt control logic shared by the plurality of TCs rather than being replicated for each of the plurality of TCs, the method further comprising:

managing the interrupt control logic only by operating system-privileged threads of the OS executing on all of the plurality of TCs rather than by user-privileged threads executing on each of the plurality of TCs.

32. The method as recited in claim 31, wherein said managing the interrupt control logic comprises disabling interrupt requests only for one of the plurality of TCs executing one of the operating-system privileged threads, rather than disabling interrupt requests for all of the plurality of TCs.

33. The method as recited in claim 28, wherein the microprocessor further includes a second plurality of thread contexts (TCs), each having a program counter and a general purpose register set for executing a thread, and a second shared privileged resource, shared only by the second plurality of TCs, and rather than being replicated for each of the second plurality of TCs, the method further comprising:

managing the second shared privileged resource only by said operating system-privileged threads of the OS executing on all of the second plurality of TCs rather than by said user-privileged threads executing on each of the second plurality of TCs.

34. The method as recited in claim 33, wherein each of the first and second shared privileged resource comprises an exception domain.

35. The method as recited in claim 34, wherein the microprocessor further comprises a translation lookaside buffer (TLB) shared by the first and second plurality of TCs rather than being replicated for each of the first and second plurality of TCs, the method further comprising:

managing the shared privileged resource by operating system-privileged threads of the OS executing on the first and second plurality of TCs rather than by user-privileged threads executing on the first and second plurality of TCs.

36. The method as recited in claim 33, wherein each of the first and second shared privileged resource comprises a TLB.

37. The method as recited in claim 28, wherein the shared privileged resource comprises an exception domain comprising a control register programmable by the OS, wherein said managing the shared privileged resource comprises programming said control register to control enablement and disablement of interrupt requests globally to all of the plurality of TCs.

38. The method as recited in claim 28, wherein the shared privileged resource comprises an exception domain comprising a status register readable by the OS, wherein said managing the shared privileged resource comprises reading the status register to determine a source of interrupt requests, wherein the interrupt requests are non-specific to the plurality of TCs, wherein the exception domain is configured to select one of the plurality of TCs to execute one of said operating-system privileged threads to service an active one of the interrupt requests to perform said reading the status register.

39. The method as recited in claim 28, wherein the shared privileged resource comprises an exception domain configured to receive interrupt requests, wherein the interrupt requests are non-specific to the plurality of TCs, wherein the exception domain is configured to select one of the plurality of TCs to execute one of said operating-system privilege level threads to service an active one of the interrupt requests, the method further comprising:

executing operating-system privileged threads on the selected one of the plurality of TCs to direct an exception to a second of the plurality of TCs by writing an address of an interrupt handler to the program counter of the second of the plurality of TCs.

40. The method as recited in claim 28, wherein the shared privileged resource comprises an exception domain configured to receive interrupt requests, wherein the interrupt requests are non-specific to the plurality of TCs, wherein the exception domain is configured to select one of the plurality of TCs to execute one of said operating-system privilege level threads to service an active one of the interrupt requests, wherein the microprocessor further comprises a translation lookaside buffer (TLB) shared by the plurality of TCs rather than being replicated for each of the plurality of TCs, the method further comprising:

managing the TLB only by operating system-privileged threads of the OS executing on all of the plurality of TCs rather than by user-privileged threads executing on each of the plurality of TCs.

41. The method as recited in claim 28, wherein the OS comprises a data structure having an entry for each of the plurality of TCs, each entry containing information describing capabilities of the corresponding one of the plurality of TCs, wherein each entry further comprises a TC identifier field for identifying a corresponding one of the plurality of TCs, the method further comprising:

populating the TC identifier field for each of the entries with a unique identifier value.

42. The method as recited in claim 41, wherein the unique identifier value is stored in a MIPS Multithreading Application Specific Extension (MT ASE) current thread context (CurTC) field in a TCBind Register.

43. The method as recited in claim 41, further comprising:

invoking a CPU probe routine only for a first of the plurality of TCs;

responsively populating the first entry with information describing the shared privileged resource; and

subsequently copying the first entry to each remaining entry of the data structure without invoking the CPU probe routine for the remaining plurality of TCs.

44. The method as recited in claim 41, wherein the multithreading microprocessor further comprises one or more virtual processing elements (VPEs), wherein each of the one or more VPEs is an exception domain for a mutually exclusive subset of one or more of the plurality of TCs, wherein each entry further comprises a VPE identifier field for identifying one of the VPEs bound to the corresponding one of the plurality of TCs, the method further comprising:

populating the VPE identifier field for each of the entries with an identifier value identifying one of the VPEs to which the corresponding one of the plurality of TCs is bound.

45. The method as recited in claim 44, wherein the unique identifier value is stored in a MIPS Multithreading Application Specific Extension (MT ASE) current VPE (CurVPE) field in a TCBind Register.

46. The method as recited in claim 44, wherein the OS is configured to invoke a per-CPU trap initialization routine only for one of the subset of TCs per one of the VPEs.

47. The method as recited in claim 28, wherein the plurality of TCs is configured as an array of thread contexts (TCs), wherein each of the plurality of TCs further comprises a register for storing an index of the respective TC within the array, wherein the OS is further configured to maintain a table of entries, each entry for storing a CPU-unique value for a respective one of the TCs, the method further comprising:

executing a respective thread on each of the respective TCs;

reading the index from the register of the respective one of the TCs; and

reading the respective CPU-unique value for the respective one of the TCs using the index.

48. The method as recited in claim 47, wherein the CPU-unique value comprises a kernel stack pointer.

49. The method as recited in claim 47, wherein the CPU-unique value comprises a page table origin.

50. The method as recited in claim 47, wherein the shared privileged resource comprises a register for indicating which of a plurality of interrupt requests is active, wherein the CPU-unique value comprises a storage location for saving and restoring the contents of the register indicating which of a plurality of interrupt requests is active.

51. The method as recited in claim 28, further comprising:

executing an instance of a thread scheduler on each of the plurality of TCs to schedule execution of the user-privileged threads on the plurality of TCs.

52. The method as recited in claim 51, further comprising:

for each of the instances of the OS;

scheduling execution of the operating system-privileged threads on the plurality of TCs to manage the shared privileged resource.

managing the shared privileged resource only by operating system-privileged threads of the OS executing on all of the plurality of TCs rather than by user-privileged threads executing on each of the plurality of TCs; and

scheduling execution of both the operating system-privileged threads and the user-privileged threads on the plurality of TCs.

53. A computer program product for use with a computing device, the computer program product comprising:

a computer usable medium, having computer readable program code embodied in said medium, for causing a method for a multiprocessor operating system (OS) to run on a multiprocessing system having a multithreading microprocessor including a plurality of thread contexts (TCs) each having a program counter and a general purpose register set for executing a thread, and a shared privileged resource shared by the plurality of TCs rather than being replicated for each of the plurality of TCs, said computer readable program code comprising;

first program code for providing a step of managing the shared privileged resource only by operating system-privileged threads of the OS executing on all of the plurality of TCs rather than by user-privileged threads executing on each of the plurality of TCs; and

second program code for providing a step of scheduling execution of both the operating system-privileged threads and the user-privileged threads on the plurality of TCs.

54. A method for providing operating system software for running on a multiprocessing system having a multithreading microprocessor including a plurality of thread contexts (TCs) each having a program counter and a general purpose register set for executing a thread, and a shared privileged resource shared by the plurality of TCs rather than being replicated for each of the plurality of TCs, the method comprising:

providing computer-readable program code describing the operating system software, the program code comprising;

first program code for providing a step of managing the shared privileged resource only by operating system-privileged threads of the OS executing on all of the plurality of TCs rather than by user-privileged threads executing on each of the plurality of TCs; and

second program code for providing a step of scheduling execution of both the operating system-privileged threads and the user-privileged threads on the plurality of TCs; and

transmitting the computer-readable program code as a computer data signal on a network.