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Dynamic clock change circuit

  • US 20070043966A1
  • Filed: 08/17/2005
  • Published: 02/22/2007
  • Est. Priority Date: 08/17/2005
  • Status: Active Grant
First Claim
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1. A circuit comprising:

  • a counter for receipt of a master clock signal;

    a multiplexer for receipt of an output of the counter, the multiplexer outputting a clock frequency to a system clock;

    a flip flop for generating an enable signal corresponding to a low frequency period of the master clock signal and for enabling a clock change request signal; and

    a NOR gate disposed between the counter and the flip flop.

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