Dynamic clock change circuit

• US 20070043966A1
• Filed: 08/17/2005
• Published: 02/22/2007
• Est. Priority Date: 08/17/2005
• Status: Active Grant

• Current Assignee: Digi International Inc.
• Original Assignee: Digi International Inc.
• Inventors: Chang, Christopher, Parker, Jeffrey
• Granted Patent: US 7,265,588 B2
• Time in Patent Office: Days
• US Class Current: 713/500
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A clock change circuit includes enabling a clock change frequency to be accepted while a system is active and clock frequencies are at a low period. The circuit includes generating an enabling signal representing a window of time in which a frequency change is accomplished.

Claims

1. A circuit comprising:

a counter for receipt of a master clock signal;

a multiplexer for receipt of an output of the counter, the multiplexer outputting a clock frequency to a system clock;

a flip flop for generating an enable signal corresponding to a low frequency period of the master clock signal and for enabling a clock change request signal; and

a NOR gate disposed between the counter and the flip flop.

2. The circuit of claim 1 wherein the counter is a synchronous counter.

3. The circuit of claim 2 wherein the synchronous counter is a 5-bit counter.

4. The circuit of claim 1 further comprising a NOR gate disposed between the counter and the flip flop.

5. The circuit of claim 1 wherein the output of the counter is a frequency signal is divided by an integer value.

6. The circuit of claim 5 wherein the integer value is selected from a group consisting of 2, 4, 8, 16 and 32.

7. A clock frequency change circuit comprising:

a synchronous counter for receipt of a master clock signal;

a first multiplexer for receipt of an output of the counter, the first multiplexer outputting a clock frequency to a first system clock;

a second multiplexer for receipt of the output of the counter, the second multiplexer outputting a clock frequency to a second system clock; and

a flip flop for generating an enable signal corresponding to a low frequency period of the master clock signal and for enabling a clock change request signal.

8. The circuit of claim 7 wherein the synchronous counter is a 5-bit counter.

9. The circuit of claim 7 further comprising a NOR gate disposed between the counter and the flip flop.

10. The circuit of claim 7 wherein the output of the counter is a frequency signal is divided by an integer value.

11. The circuit of claim 10 wherein the integer value is selected from a group consisting of 2, 4, 8, 16 and 32.

12. A method of changing a clock frequency of a system clock comprising:

receiving a clock frequency change request signal;

generating an enabling signal in a flip flop corresponding to a low period of clock signals entering a multiplexer;

receiving a master clock signal in the flip flop; and

sending the clock frequency change signal to the multiplexer at the time indicated by the enabling signal.

13. The circuit of claim 12 wherein the counter is a synchronous counter.

14. The circuit of claim 13 wherein the synchronous counter is a 5-bit counter.

15. The method of claim 12 further comprising outputting a signal from the multiplexer to a system clock.