Configurable voltage regulator

• US 20070043987A1
• Filed: 10/12/2006
• Published: 02/22/2007
• Est. Priority Date: 09/19/2002
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Sehat Sutardja
• Inventors: Sutardja, Sehat
• Granted Patent: US 7,480,578 B2
• Time in Patent Office: Days
• US Class Current: 714/724
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/31721 Power aspects, e.g. power supplies for test circuits, power saving during test for scan test G01R31/318575
• CPC Class Codes: G01R 31/31908 Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50008 of impedance

Abstract

A testing system comprises a configurable integrated circuit that has M predetermined configurations that are selected based upon an input signal. The configurable integrated circuit generates a selected one of M discrete values of an output characteristic of the configurable integrated circuit based on the selected one of the M predetermined configurations, where M is an integer greater than one. An integrated circuit is tested in accordance with an output of the configurable integrated circuit.

Claims

1. A testing system comprising:

a configurable integrated circuit that has M predetermined configurations that are selected based upon an input signal,

wherein said configurable integrated circuit generates a selected one of M discrete values of an output characteristic of said configurable integrated circuit based on said selected one of said M predetermined configurations, where M is an integer greater than one; and

an integrated circuit that is tested in accordance with an output of said configurable integrated circuit.

2. The testing system of claim 1 wherein said integrated circuit includes at least one of a memory circuit and a central processing unit.

3. The testing system of claim 1 further comprising a test module that tests operation of said integrated circuit while said integrated circuit operates based upon at least two of said M discrete values of said output characteristic.

4. The testing system of claim 3 wherein said test module is integrated with said integrated circuit.

5. The testing system of claim 3 wherein said test module communicates with said integrated circuit.

6. The testing system of claim 1 further comprising a selector control module that generates said input signal.

7. The testing system of claim 6 wherein said input signal includes a up signal that increases said selected one of said M discrete values of said external characteristic and a down signal that decreases said selected one of said M discrete values of said external characteristic.

8. The testing system of claim 1 further comprising:

P additional configurable integrated circuits that communicate with said configurable integrated circuit in a daisy chain configuration; and

P additional circuits that communicate with a respective one of said P additional configurable integrated circuits.

9. A method for testing comprising:

providing a configurable integrated circuit that has M predetermined configurations;

selecting one of said M predetermined configurations based upon an input signal;

generating a selected one of M discrete values of an output characteristic of said configurable integrated circuit based on said selected one of said M predetermined configurations, where M is an integer greater than one; and

testing an integrated circuit in accordance with an output of said configurable integrated circuit.

10. The method of claim 9 wherein said integrated circuit includes at least one of a memory circuit and a central processing unit.

11. The method of claim 9 further comprising testing operation of said integrated circuit while said integrated circuit operates based upon at least two of said M discrete values of said output characteristic.

12. The method of claim 11 further comprising integrating said test module integrated with said integrated circuit.

13. The method of claim 9 further comprising generating said input signal, wherein said input signal includes a up signal that increases said selected one of said M discrete values of said external characteristic and a down signal that decreases said selected one of said M discrete values of said external characteristic.

14. The method of claim 9 further comprising:

providing P additional configurable integrated circuits that communicate with said configurable integrated circuit in a daisy chain configuration; and

providing P additional circuits that communicate with a respective one of said P additional configurable integrated circuits.

15. A testing system comprising:

configurable integrated circuit means for providing M predetermined configurations that are selected based upon an input signal,

wherein said configurable integrated circuit means generates a selected one of M discrete values of an output characteristic of said configurable integrated circuit means based on said selected one of said M predetermined configurations, where M is an integer greater than one; and

integrated circuit means that is tested in accordance with an output of said configurable integrated circuit means.

16. The testing system of claim 15 wherein said integrated circuit means includes at least one of storing means for storing data and processing means for processing data.

17. The testing system of claim 15 further comprising test means for testing operation of said integrated circuit means while said integrated circuit means operates based upon at least two of said M discrete values of said output characteristic.

18. The testing system of claim 17 wherein said test means is integrated with said integrated circuit means.

19. The testing system of claim 17 wherein said test means communicates with said integrated circuit means.

20. The testing system of claim 15 further comprising selector control means for generating said input signal.

21. The testing system of claim 20 wherein said input signal includes a up signal that increases said selected one of said M discrete values of said external characteristic and a down signal that decreases said selected one of said M discrete values of said external characteristic.

22. The testing system of claim 15 further comprising:

P additional configurable integrated circuit means for communicating with said configurable integrated circuit means in a daisy chain configuration; and

P additional circuit means that communicate with a respective one of said P additional configurable integrated circuit means.