System and method for protection of data contained in an integrated circuit

• US 20070043993A1
• Filed: 04/11/2006
• Published: 02/22/2007
• Est. Priority Date: 04/11/2005
• Status: Active Grant

• Current Assignee: Stmicroelectronics France (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Inventors: Pomet, Alain, Romain, Fabrice
• Granted Patent: US 7,806,319 B2
• Time in Patent Office: Days
• US Class Current: 714/736
• CPC Class Codes: G06F 21/77 in smart cards
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories
• CPC Class Codes: G06K 19/073 Special arrangements for circuits, e.g. for protecting identification code in memory protection against unauthorised use of computer memory G06F12/14
• CPC Class Codes: G06Q 20/341 Active cards, i.e. cards including their own processing means, e.g. including an IC or chip
• CPC Class Codes: G07F 7/082 Features insuring the integrity of the data on or in the card
• CPC Class Codes: G07F 7/1008 Active credit-cards provided with means to personalise their use, e.g. with PIN-introduction/comparison system
• CPC Class Codes: H04L 9/004 for fault attacks

Abstract

A method and a circuit for protecting an integrated circuit against an extraction of data read from at least one memory, comprising the steps of comparing each data word to be output from the integrated circuit with at least one value stored in this circuit, and generating an error signal in case of an identity between the value and the data waiting to be output.

Claims

1. A method for protecting an integrated circuit against an extraction of data read from at least one memory, comprising the steps of:

comparing each data word to be output from the integrated circuit with at least one value stored in this circuit, said value being stored at several locations in the memory at addresses which are not likely to be requested by programs providing data to the outside of the circuit; and

generating an error signal in case of an identity between the value and the data waiting to be output.

2. The method of claim 1, wherein said value is stored in an element distinct from said memory.

3. The method of claim 2, wherein said value is stored in non-volatile fashion, preferably, by hardware writing.

4. The method of claim 1, wherein the address of a data word to be read from the memory to be provided to the outside of the circuit is compared with at least one address stored in the circuit, said error signal being generated in case of an identity between the two addresses.

15. The method of claim 1, wherein each value is stored in an element distinct from said memory.

5. An integrated circuit comprising at least a central processing unit, a memory, an input/output circuit, and comprising at least one circuit comprising at least one element for storing a first data word and a comparator of a second data word, provided by an internal bus, with respect to said first word.

6. The circuit of claim 5, wherein said detection circuit comprises means for generating an error signal in case of an identity between said data words.

7. The circuit of claim 5, wherein an address storage element is contained in the detection circuit.

8. A smart card containing the integrated circuit of claim 5.

9. A method of protecting data stored in an integrated circuit against undesired output of that data from the integrated circuit, the method comprising:

storing at least one value in the integrated circuit, each value being stored at a plurality of locations in the integrated circuit with each location being a location that is unlikely to be accessed during the output of data from the integrated circuit;

for data to be output from the integrated circuit, comparing the data to at least one value stored in the integrated circuit; and

when the operation of comparing indicates the data equals one of the stored values, prohibiting the output of the data from the integrated circuit.

10. The method of claim 9 wherein the data being compared to the predetermined values comprises an address associated with a data word stored in the integrated circuit.

11. The method of claim 10 wherein the data being compared comprises both the address and the data word, with the address being compared to predetermined address values and the data word being compared to predetermined data word values.

12. The method of claim 9 wherein prohibiting the output of the data word from the integrated circuit includes generating an error signal.

13. The method of claim 9 wherein each location comprises non-volatile memory storage location.

14. The method of claim 9 wherein the values stored in the integrated circuit have predetermined values determined by a user of the integrated circuit.

16. An integrated circuit, comprising:

a processor;

a memory coupled to the processor, the memory operable to store data words; and

an input/output circuit coupled to the processor, the input/output circuit operable to compare data words received from the memory via the processor to at least one prohibited value, each prohibited value being stored in a plurality of storage locations in the integrated circuit and the input/output circuit operable to prevent the data word from being output from the integrated circuit responsive to the data word being equal to one of the prohibited values.

17. The integrated circuit of claim 16 wherein the input/output circuit comprises:

at least one storage element, each storage element storing a respective prohibited value; and

a comparator coupled to each storage element and to the processor, the comparator coupled to receive data words from the processor and operable to compare the data words to the prohibited values in the storage elements and to generate an alarm signal responsive to the data word being equal to any of the prohibited values.

18. The integrated circuit of claim 17 wherein the storage element and comparator are physically positioned adjacent circuitry in the input/output circuitry that outputs data words from the integrated circuit.

19. The integrated circuit of claim 17 wherein each data word stored in the memory has an associated address and wherein the prohibited values include prohibited address values, and wherein the comparator is further operable to compare the address of each data word to the prohibited address values and to generate the alarm signal responsive to the address being equal to any of the prohibited address values.

20. The integrated circuit of claim 16 wherein the integrated circuit comprises a smart card.

21. The integrated circuit of claim 20 wherein the smart card comprises a telephone calling or electronic cash payments smart card.

22. The integrated circuit of claim 16 wherein the input/output circuit includes storage locations and the prohibited values are stored in these storage elements in the input/output circuit.

23. The integrated circuit of claim 22 wherein the prohibited values have values with a low probability of occurring in other data words stored in the memory.

24. The integrated circuit of claim 16 wherein the prohibited values are stored in storage locations in the memory.